diff options
Diffstat (limited to 'pvr-source/services4/srvkm/hwdefs')
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/mnemedefs.h | 117 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/ocpdefs.h | 308 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgx520defs.h | 555 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgx530defs.h | 542 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgx531defs.h | 601 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgx535defs.h | 739 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgx540defs.h | 605 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgx543_v1.164defs.h | 1396 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgx543defs.h | 1487 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgx544defs.h | 1487 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgx545defs.h | 1290 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgxdefs.h | 112 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgxerrata.h | 495 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgxfeaturedefs.h | 274 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgxmmu.h | 99 | ||||
| -rwxr-xr-x | pvr-source/services4/srvkm/hwdefs/sgxmpdefs.h | 365 |
16 files changed, 0 insertions, 10472 deletions
diff --git a/pvr-source/services4/srvkm/hwdefs/mnemedefs.h b/pvr-source/services4/srvkm/hwdefs/mnemedefs.h deleted file mode 100755 index 83a65f5..0000000 --- a/pvr-source/services4/srvkm/hwdefs/mnemedefs.h +++ /dev/null @@ -1,117 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for MNEME. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _MNEMEDEFS_KM_H_ -#define _MNEMEDEFS_KM_H_ - -/* Register MNE_CR_CTRL */ -#define MNE_CR_CTRL 0x0D00 -#define MNE_CR_CTRL_BYP_CC_N_MASK 0x00010000U -#define MNE_CR_CTRL_BYP_CC_N_SHIFT 16 -#define MNE_CR_CTRL_BYP_CC_N_SIGNED 0 -#define MNE_CR_CTRL_BYP_CC_MASK 0x00008000U -#define MNE_CR_CTRL_BYP_CC_SHIFT 15 -#define MNE_CR_CTRL_BYP_CC_SIGNED 0 -#define MNE_CR_CTRL_USE_INVAL_REQ_MASK 0x00007800U -#define MNE_CR_CTRL_USE_INVAL_REQ_SHIFT 11 -#define MNE_CR_CTRL_USE_INVAL_REQ_SIGNED 0 -#define MNE_CR_CTRL_BYPASS_ALL_MASK 0x00000400U -#define MNE_CR_CTRL_BYPASS_ALL_SHIFT 10 -#define MNE_CR_CTRL_BYPASS_ALL_SIGNED 0 -#define MNE_CR_CTRL_BYPASS_MASK 0x000003E0U -#define MNE_CR_CTRL_BYPASS_SHIFT 5 -#define MNE_CR_CTRL_BYPASS_SIGNED 0 -#define MNE_CR_CTRL_PAUSE_MASK 0x00000010U -#define MNE_CR_CTRL_PAUSE_SHIFT 4 -#define MNE_CR_CTRL_PAUSE_SIGNED 0 -/* Register MNE_CR_USE_INVAL */ -#define MNE_CR_USE_INVAL 0x0D04 -#define MNE_CR_USE_INVAL_ADDR_MASK 0xFFFFFFFFU -#define MNE_CR_USE_INVAL_ADDR_SHIFT 0 -#define MNE_CR_USE_INVAL_ADDR_SIGNED 0 -/* Register MNE_CR_STAT */ -#define MNE_CR_STAT 0x0D08 -#define MNE_CR_STAT_PAUSED_MASK 0x00000400U -#define MNE_CR_STAT_PAUSED_SHIFT 10 -#define MNE_CR_STAT_PAUSED_SIGNED 0 -#define MNE_CR_STAT_READS_MASK 0x000003FFU -#define MNE_CR_STAT_READS_SHIFT 0 -#define MNE_CR_STAT_READS_SIGNED 0 -/* Register MNE_CR_STAT_STATS */ -#define MNE_CR_STAT_STATS 0x0D0C -#define MNE_CR_STAT_STATS_RST_MASK 0x000FFFF0U -#define MNE_CR_STAT_STATS_RST_SHIFT 4 -#define MNE_CR_STAT_STATS_RST_SIGNED 0 -#define MNE_CR_STAT_STATS_SEL_MASK 0x0000000FU -#define MNE_CR_STAT_STATS_SEL_SHIFT 0 -#define MNE_CR_STAT_STATS_SEL_SIGNED 0 -/* Register MNE_CR_STAT_STATS_OUT */ -#define MNE_CR_STAT_STATS_OUT 0x0D10 -#define MNE_CR_STAT_STATS_OUT_VALUE_MASK 0xFFFFFFFFU -#define MNE_CR_STAT_STATS_OUT_VALUE_SHIFT 0 -#define MNE_CR_STAT_STATS_OUT_VALUE_SIGNED 0 -/* Register MNE_CR_EVENT_STATUS */ -#define MNE_CR_EVENT_STATUS 0x0D14 -#define MNE_CR_EVENT_STATUS_INVAL_MASK 0x00000001U -#define MNE_CR_EVENT_STATUS_INVAL_SHIFT 0 -#define MNE_CR_EVENT_STATUS_INVAL_SIGNED 0 -/* Register MNE_CR_EVENT_CLEAR */ -#define MNE_CR_EVENT_CLEAR 0x0D18 -#define MNE_CR_EVENT_CLEAR_INVAL_MASK 0x00000001U -#define MNE_CR_EVENT_CLEAR_INVAL_SHIFT 0 -#define MNE_CR_EVENT_CLEAR_INVAL_SIGNED 0 -/* Register MNE_CR_CTRL_INVAL */ -#define MNE_CR_CTRL_INVAL 0x0D20 -#define MNE_CR_CTRL_INVAL_PREQ_PDS_MASK 0x00000008U -#define MNE_CR_CTRL_INVAL_PREQ_PDS_SHIFT 3 -#define MNE_CR_CTRL_INVAL_PREQ_PDS_SIGNED 0 -#define MNE_CR_CTRL_INVAL_PREQ_USEC_MASK 0x00000004U -#define MNE_CR_CTRL_INVAL_PREQ_USEC_SHIFT 2 -#define MNE_CR_CTRL_INVAL_PREQ_USEC_SIGNED 0 -#define MNE_CR_CTRL_INVAL_PREQ_CACHE_MASK 0x00000002U -#define MNE_CR_CTRL_INVAL_PREQ_CACHE_SHIFT 1 -#define MNE_CR_CTRL_INVAL_PREQ_CACHE_SIGNED 0 -#define MNE_CR_CTRL_INVAL_ALL_MASK 0x00000001U -#define MNE_CR_CTRL_INVAL_ALL_SHIFT 0 -#define MNE_CR_CTRL_INVAL_ALL_SIGNED 0 - -#endif /* _MNEMEDEFS_KM_H_ */ - diff --git a/pvr-source/services4/srvkm/hwdefs/ocpdefs.h b/pvr-source/services4/srvkm/hwdefs/ocpdefs.h deleted file mode 100755 index 07a6412..0000000 --- a/pvr-source/services4/srvkm/hwdefs/ocpdefs.h +++ /dev/null @@ -1,308 +0,0 @@ -/*************************************************************************/ /*! -@Title OCP HW definitions. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _OCPDEFS_H_ -#define _OCPDEFS_H_ - -/* Register EUR_CR_OCP_REVISION */ -#define EUR_CR_OCP_REVISION 0xFE00 -#define EUR_CR_OCP_REVISION_REV_MASK 0xFFFFFFFFUL -#define EUR_CR_OCP_REVISION_REV_SHIFT 0 -#define EUR_CR_OCP_REVISION_REV_SIGNED 0 - -/* Register EUR_CR_OCP_HWINFO */ -#define EUR_CR_OCP_HWINFO 0xFE04 -#define EUR_CR_OCP_HWINFO_SYS_BUS_WIDTH_MASK 0x00000003UL -#define EUR_CR_OCP_HWINFO_SYS_BUS_WIDTH_SHIFT 0 -#define EUR_CR_OCP_HWINFO_SYS_BUS_WIDTH_SIGNED 0 - -#define EUR_CR_OCP_HWINFO_MEM_BUS_WIDTH_MASK 0x00000004UL -#define EUR_CR_OCP_HWINFO_MEM_BUS_WIDTH_SHIFT 2 -#define EUR_CR_OCP_HWINFO_MEM_BUS_WIDTH_SIGNED 0 - -/* Register EUR_CR_OCP_SYSCONFIG */ -#define EUR_CR_OCP_SYSCONFIG 0xFE10 -#define EUR_CR_OCP_SYSCONFIG_IDLE_MODE_MASK 0x0000000CUL -#define EUR_CR_OCP_SYSCONFIG_IDLE_MODE_SHIFT 2 -#define EUR_CR_OCP_SYSCONFIG_IDLE_MODE_SIGNED 0 - -#define EUR_CR_OCP_SYSCONFIG_STANDBY_MODE_MASK 0x00000030UL -#define EUR_CR_OCP_SYSCONFIG_STANDBY_MODE_SHIFT 4 -#define EUR_CR_OCP_SYSCONFIG_STANDBY_MODE_SIGNED 0 - -/* Register EUR_CR_OCP_IRQSTATUS_RAW_0 */ -#define EUR_CR_OCP_IRQSTATUS_RAW_0 0xFE24 -#define EUR_CR_OCP_IRQSTATUS_RAW_0_INIT_MASK 0x00000001UL -#define EUR_CR_OCP_IRQSTATUS_RAW_0_INIT_SHIFT 0 -#define EUR_CR_OCP_IRQSTATUS_RAW_0_INIT_SIGNED 0 - -/* Register EUR_CR_OCP_IRQSTATUS_RAW_1 */ -#define EUR_CR_OCP_IRQSTATUS_RAW_1 0xFE28 -#define EUR_CR_OCP_IRQSTATUS_RAW_1_TARGET_MASK 0x00000001UL -#define EUR_CR_OCP_IRQSTATUS_RAW_1_TARGET_SHIFT 0 -#define EUR_CR_OCP_IRQSTATUS_RAW_1_TARGET_SIGNED 0 - -/* Register EUR_CR_OCP_IRQSTATUS_RAW_2 */ -#define EUR_CR_OCP_IRQSTATUS_RAW_2 0xFE2C -#define EUR_CR_OCP_IRQSTATUS_RAW_2_SGXCORE_MASK 0x00000001UL -#define EUR_CR_OCP_IRQSTATUS_RAW_2_SGXCORE_SHIFT 0 -#define EUR_CR_OCP_IRQSTATUS_RAW_2_SGXCORE_SIGNED 0 - -/* Register EUR_CR_OCP_IRQSTATUS_0 */ -#define EUR_CR_OCP_IRQSTATUS_0 0xFE30 -#define EUR_CR_OCP_IRQSTATUS_0_INIT_MASK 0x00000001UL -#define EUR_CR_OCP_IRQSTATUS_0_INIT_SHIFT 0 -#define EUR_CR_OCP_IRQSTATUS_0_INIT_SIGNED 0 - -/* Register EUR_CR_OCP_IRQSTATUS_1 */ -#define EUR_CR_OCP_IRQSTATUS_1 0xFE34 -#define EUR_CR_OCP_IRQSTATUS_1_TARGET_MASK 0x00000001UL -#define EUR_CR_OCP_IRQSTATUS_1_TARGET_SHIFT 0 -#define EUR_CR_OCP_IRQSTATUS_1_TARGET_SIGNED 0 - -/* Register EUR_CR_OCP_IRQSTATUS_2 */ -#define EUR_CR_OCP_IRQSTATUS_2 0xFE38 -#define EUR_CR_OCP_IRQSTATUS_2_SGXCORE_MASK 0x00000001UL -#define EUR_CR_OCP_IRQSTATUS_2_SGXCORE_SHIFT 0 -#define EUR_CR_OCP_IRQSTATUS_2_SGXCORE_SIGNED 0 - -/* Register EUR_CR_OCP_IRQENABLE_SET_0 */ -#define EUR_CR_OCP_IRQENABLE_SET_0 0xFE3C -#define EUR_CR_OCP_IRQENABLE_SET_0_INIT_MASK 0x00000001UL -#define EUR_CR_OCP_IRQENABLE_SET_0_INIT_SHIFT 0 -#define EUR_CR_OCP_IRQENABLE_SET_0_INIT_SIGNED 0 - -/* Register EUR_CR_OCP_IRQENABLE_SET_1 */ -#define EUR_CR_OCP_IRQENABLE_SET_1 0xFE40 -#define EUR_CR_OCP_IRQENABLE_SET_1_TARGET_MASK 0x00000001UL -#define EUR_CR_OCP_IRQENABLE_SET_1_TARGET_SHIFT 0 -#define EUR_CR_OCP_IRQENABLE_SET_1_TARGET_SIGNED 0 - -/* Register EUR_CR_OCP_IRQENABLE_SET_2 */ -#define EUR_CR_OCP_IRQENABLE_SET_2 0xFE44 -#define EUR_CR_OCP_IRQENABLE_SET_2_SGXCORE_MASK 0x00000001UL -#define EUR_CR_OCP_IRQENABLE_SET_2_SGXCORE_SHIFT 0 -#define EUR_CR_OCP_IRQENABLE_SET_2_SGXCORE_SIGNED 0 - -/* Register EUR_CR_OCP_IRQENABLE_CLR_0 */ -#define EUR_CR_OCP_IRQENABLE_CLR_0 0xFE48 -#define EUR_CR_OCP_IRQENABLE_CLR_0_INIT_MASK 0x00000001UL -#define EUR_CR_OCP_IRQENABLE_CLR_0_INIT_SHIFT 0 -#define EUR_CR_OCP_IRQENABLE_CLR_0_INIT_SIGNED 0 - -/* Register EUR_CR_OCP_IRQENABLE_CLR_1 */ -#define EUR_CR_OCP_IRQENABLE_CLR_1 0xFE4C -#define EUR_CR_OCP_IRQENABLE_CLR_1_TARGET_MASK 0x00000001UL -#define EUR_CR_OCP_IRQENABLE_CLR_1_TARGET_SHIFT 0 -#define EUR_CR_OCP_IRQENABLE_CLR_1_TARGET_SIGNED 0 - -/* Register EUR_CR_OCP_IRQENABLE_CLR_2 */ -#define EUR_CR_OCP_IRQENABLE_CLR_2 0xFE50 -#define EUR_CR_OCP_IRQENABLE_CLR_2_SGXCORE_MASK 0x00000001UL -#define EUR_CR_OCP_IRQENABLE_CLR_2_SGXCORE_SHIFT 0 -#define EUR_CR_OCP_IRQENABLE_CLR_2_SGXCORE_SIGNED 0 - -/* Register EUR_CR_OCP_PAGE_CONFIG */ -#define EUR_CR_OCP_PAGE_CONFIG 0xFF00 -#define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_SIZE_MASK 0x00000001UL -#define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_SIZE_SHIFT 0 -#define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_SIZE_SIGNED 0 - -#define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_CHECK_ENABLE_MASK 0x00000004UL -#define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_CHECK_ENABLE_SHIFT 2 -#define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_CHECK_ENABLE_SIGNED 0 - -#define EUR_CR_OCP_PAGE_CONFIG_SIZE_MASK 0x00000018UL -#define EUR_CR_OCP_PAGE_CONFIG_SIZE_SHIFT 3 -#define EUR_CR_OCP_PAGE_CONFIG_SIZE_SIGNED 0 - -/* Register EUR_CR_OCP_INTERRUPT_EVENT */ -#define EUR_CR_OCP_INTERRUPT_EVENT 0xFF04 -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_MASK 0x00000001UL -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_SHIFT 0 -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_SIGNED 0 - -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_MASK 0x00000002UL -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_SHIFT 1 -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_SIGNED 0 - -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_ERROR_MASK 0x00000004UL -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_ERROR_SHIFT 2 -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_ERROR_SIGNED 0 - -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_MASK 0x00000008UL -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_SHIFT 3 -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_SIGNED 0 - -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVR_MASK 0x00000010UL -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVR_SHIFT 4 -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVR_SIGNED 0 - -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_MEM_REQ_FIFO_OVR_MASK 0x00000020UL -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_MEM_REQ_FIFO_OVR_SHIFT 5 -#define EUR_CR_OCP_INTERRUPT_EVENT_INIT_MEM_REQ_FIFO_OVR_SIGNED 0 - -#define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_RESP_FIFO_FULL_MASK 0x00000100UL -#define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_RESP_FIFO_FULL_SHIFT 8 -#define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_RESP_FIFO_FULL_SIGNED 0 - -#define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_CMD_FIFO_FULL_MASK 0x00000200UL -#define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_CMD_FIFO_FULL_SHIFT 9 -#define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_CMD_FIFO_FULL_SIGNED 0 - -#define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_MASK 0x00000400UL -#define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_SHIFT 10 -#define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_SIGNED 0 - -/* Register EUR_CR_OCP_DEBUG_CONFIG */ -#define EUR_CR_OCP_DEBUG_CONFIG 0xFF08 -#define EUR_CR_OCP_DEBUG_CONFIG_FORCE_TARGET_IDLE_MASK 0x00000003UL -#define EUR_CR_OCP_DEBUG_CONFIG_FORCE_TARGET_IDLE_SHIFT 0 -#define EUR_CR_OCP_DEBUG_CONFIG_FORCE_TARGET_IDLE_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_CONFIG_FORCE_INIT_IDLE_MASK 0x0000000CUL -#define EUR_CR_OCP_DEBUG_CONFIG_FORCE_INIT_IDLE_SHIFT 2 -#define EUR_CR_OCP_DEBUG_CONFIG_FORCE_INIT_IDLE_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_CONFIG_FORCE_PASS_DATA_MASK 0x00000010UL -#define EUR_CR_OCP_DEBUG_CONFIG_FORCE_PASS_DATA_SHIFT 4 -#define EUR_CR_OCP_DEBUG_CONFIG_FORCE_PASS_DATA_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_CONFIG_SELECT_INIT_IDLE_MASK 0x00000020UL -#define EUR_CR_OCP_DEBUG_CONFIG_SELECT_INIT_IDLE_SHIFT 5 -#define EUR_CR_OCP_DEBUG_CONFIG_SELECT_INIT_IDLE_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_MASK 0x80000000UL -#define EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_SHIFT 31 -#define EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_SIGNED 0 - -/* Register EUR_CR_OCP_DEBUG_STATUS */ -#define EUR_CR_OCP_DEBUG_STATUS 0xFF0C -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_MCONNECT_MASK 0x00000003UL -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_MCONNECT_SHIFT 0 -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_MCONNECT_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SCONNECT_MASK 0x00000004UL -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SCONNECT_SHIFT 2 -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SCONNECT_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEREQ_MASK 0x00000008UL -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEREQ_SHIFT 3 -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEREQ_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SDISCACK_MASK 0x00000030UL -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SDISCACK_SHIFT 4 -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SDISCACK_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEACK_MASK 0x000000C0UL -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEACK_SHIFT 6 -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEACK_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MCONNECT0_MASK 0x00000300UL -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MCONNECT0_SHIFT 8 -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MCONNECT0_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT0_MASK 0x00000400UL -#define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT0_SHIFT 10 -#define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT0_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT1_MASK 0x00000800UL -#define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT1_SHIFT 11 -#define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT1_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT2_MASK 0x00001000UL -#define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT2_SHIFT 12 -#define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT2_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCACK_MASK 0x00006000UL -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCACK_SHIFT 13 -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCACK_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCREQ_MASK 0x00008000UL -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCREQ_SHIFT 15 -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCREQ_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MWAIT_MASK 0x00010000UL -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MWAIT_SHIFT 16 -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MWAIT_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MSTANDBY_MASK 0x00020000UL -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MSTANDBY_SHIFT 17 -#define EUR_CR_OCP_DEBUG_STATUS_INIT_MSTANDBY_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_CMD_OUT_MASK 0x001C0000UL -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_CMD_OUT_SHIFT 18 -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_CMD_OUT_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_WHICH_TARGET_REGISTER_MASK 0x03E00000UL -#define EUR_CR_OCP_DEBUG_STATUS_WHICH_TARGET_REGISTER_SHIFT 21 -#define EUR_CR_OCP_DEBUG_STATUS_WHICH_TARGET_REGISTER_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_RESP_ERROR_MASK 0x04000000UL -#define EUR_CR_OCP_DEBUG_STATUS_RESP_ERROR_SHIFT 26 -#define EUR_CR_OCP_DEBUG_STATUS_RESP_ERROR_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_CMD_FIFO_FULL_MASK 0x08000000UL -#define EUR_CR_OCP_DEBUG_STATUS_CMD_FIFO_FULL_SHIFT 27 -#define EUR_CR_OCP_DEBUG_STATUS_CMD_FIFO_FULL_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_RESP_FIFO_FULL_MASK 0x10000000UL -#define EUR_CR_OCP_DEBUG_STATUS_RESP_FIFO_FULL_SHIFT 28 -#define EUR_CR_OCP_DEBUG_STATUS_RESP_FIFO_FULL_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_IDLE_MASK 0x20000000UL -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_IDLE_SHIFT 29 -#define EUR_CR_OCP_DEBUG_STATUS_TARGET_IDLE_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_CMD_RESP_DEBUG_STATE_MASK 0x40000000UL -#define EUR_CR_OCP_DEBUG_STATUS_CMD_RESP_DEBUG_STATE_SHIFT 30 -#define EUR_CR_OCP_DEBUG_STATUS_CMD_RESP_DEBUG_STATE_SIGNED 0 - -#define EUR_CR_OCP_DEBUG_STATUS_CMD_DEBUG_STATE_MASK 0x80000000UL -#define EUR_CR_OCP_DEBUG_STATUS_CMD_DEBUG_STATE_SHIFT 31 -#define EUR_CR_OCP_DEBUG_STATUS_CMD_DEBUG_STATE_SIGNED 0 - - -#endif /* _OCPDEFS_H_ */ - -/***************************************************************************** - End of file (ocpdefs.h) -*****************************************************************************/ diff --git a/pvr-source/services4/srvkm/hwdefs/sgx520defs.h b/pvr-source/services4/srvkm/hwdefs/sgx520defs.h deleted file mode 100755 index 80c3363..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgx520defs.h +++ /dev/null @@ -1,555 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for SGX520. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGX520DEFS_KM_H_ -#define _SGX520DEFS_KM_H_ - -/* Register EUR_CR_CLKGATECTL */ -#define EUR_CR_CLKGATECTL 0x0000 -#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL_USE_CLKG_MASK 0x00300000U -#define EUR_CR_CLKGATECTL_USE_CLKG_SHIFT 20 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 -/* Register EUR_CR_CLKGATESTATUS */ -#define EUR_CR_CLKGATESTATUS 0x0004 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000010U -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 4 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000100U -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 8 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00001000U -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 12 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00010000U -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 16 -#define EUR_CR_CLKGATESTATUS_USE_CLKS_MASK 0x00100000U -#define EUR_CR_CLKGATESTATUS_USE_CLKS_SHIFT 20 -/* Register EUR_CR_CLKGATECTLOVR */ -#define EUR_CR_CLKGATECTLOVR 0x0008 -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000030U -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 4 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000300U -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 8 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x00003000U -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 12 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00030000U -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 16 -#define EUR_CR_CLKGATECTLOVR_USE_CLKO_MASK 0x00300000U -#define EUR_CR_CLKGATECTLOVR_USE_CLKO_SHIFT 20 -/* Register EUR_CR_CORE_ID */ -#define EUR_CR_CORE_ID 0x0010 -#define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU -#define EUR_CR_CORE_ID_CONFIG_SHIFT 0 -#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U -#define EUR_CR_CORE_ID_ID_SHIFT 16 -/* Register EUR_CR_CORE_REVISION */ -#define EUR_CR_CORE_REVISION 0x0014 -#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU -#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 -#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U -#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8 -#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U -#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 -#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U -#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 -/* Register EUR_CR_DESIGNER_REV_FIELD1 */ -#define EUR_CR_DESIGNER_REV_FIELD1 0x0018 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 -/* Register EUR_CR_DESIGNER_REV_FIELD2 */ -#define EUR_CR_DESIGNER_REV_FIELD2 0x001C -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 -/* Register EUR_CR_SOFT_RESET */ -#define EUR_CR_SOFT_RESET 0x0080 -#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U -#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 -#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U -#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 -#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00000008U -#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 3 -#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00000010U -#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 4 -#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U -#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5 -#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000040U -#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 6 -/* Register EUR_CR_EVENT_HOST_ENABLE2 */ -#define EUR_CR_EVENT_HOST_ENABLE2 0x0110 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_CLEAR2 */ -#define EUR_CR_EVENT_HOST_CLEAR2 0x0114 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_STATUS2 */ -#define EUR_CR_EVENT_STATUS2 0x0118 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_STATUS */ -#define EUR_CR_EVENT_STATUS 0x012C -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_STATUS_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_STATUS_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_ENABLE */ -#define EUR_CR_EVENT_HOST_ENABLE 0x0130 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_CLEAR */ -#define EUR_CR_EVENT_HOST_CLEAR 0x0134 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_TIMER */ -#define EUR_CR_TIMER 0x0144 -#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU -#define EUR_CR_TIMER_VALUE_SHIFT 0 -/* Register EUR_CR_USE_CODE_BASE_0 */ -#define EUR_CR_USE_CODE_BASE_0 0x0A0C -#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_1 */ -#define EUR_CR_USE_CODE_BASE_1 0x0A10 -#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_2 */ -#define EUR_CR_USE_CODE_BASE_2 0x0A14 -#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_3 */ -#define EUR_CR_USE_CODE_BASE_3 0x0A18 -#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_4 */ -#define EUR_CR_USE_CODE_BASE_4 0x0A1C -#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_5 */ -#define EUR_CR_USE_CODE_BASE_5 0x0A20 -#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_6 */ -#define EUR_CR_USE_CODE_BASE_6 0x0A24 -#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_7 */ -#define EUR_CR_USE_CODE_BASE_7 0x0A28 -#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_8 */ -#define EUR_CR_USE_CODE_BASE_8 0x0A2C -#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_9 */ -#define EUR_CR_USE_CODE_BASE_9 0x0A30 -#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_10 */ -#define EUR_CR_USE_CODE_BASE_10 0x0A34 -#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_11 */ -#define EUR_CR_USE_CODE_BASE_11 0x0A38 -#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_12 */ -#define EUR_CR_USE_CODE_BASE_12 0x0A3C -#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_13 */ -#define EUR_CR_USE_CODE_BASE_13 0x0A40 -#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_14 */ -#define EUR_CR_USE_CODE_BASE_14 0x0A44 -#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 20 -/* Register EUR_CR_USE_CODE_BASE_15 */ -#define EUR_CR_USE_CODE_BASE_15 0x0A48 -#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 20 -/* Register EUR_CR_PDS_EXEC_BASE */ -#define EUR_CR_PDS_EXEC_BASE 0x0AB8 -#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_EVENT_KICKER */ -#define EUR_CR_EVENT_KICKER 0x0AC4 -#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0x0FFFFFF0U -#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 -/* Register EUR_CR_EVENT_KICK */ -#define EUR_CR_EVENT_KICK 0x0AC8 -#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK_NOW_SHIFT 0 -/* Register EUR_CR_EVENT_TIMER */ -#define EUR_CR_EVENT_TIMER 0x0ACC -#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U -#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 -#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU -#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 -/* Register EUR_CR_PDS_INV0 */ -#define EUR_CR_PDS_INV0 0x0AD0 -#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV0_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV1 */ -#define EUR_CR_PDS_INV1 0x0AD4 -#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV1_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV2 */ -#define EUR_CR_PDS_INV2 0x0AD8 -#define EUR_CR_PDS_INV2_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV2_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV3 */ -#define EUR_CR_PDS_INV3 0x0ADC -#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV3_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV_CSC */ -#define EUR_CR_PDS_INV_CSC 0x0AE0 -#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U -#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 -/* Register EUR_CR_PDS_PC_BASE */ -#define EUR_CR_PDS_PC_BASE 0x0B2C -#define EUR_CR_PDS_PC_BASE_ADDRESS_MASK 0x3FFFFFFFU -#define EUR_CR_PDS_PC_BASE_ADDRESS_SHIFT 0 -/* Register EUR_CR_BIF_CTRL */ -#define EUR_CR_BIF_CTRL 0x0C00 -#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U -#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 -#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U -#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1 -#define EUR_CR_BIF_CTRL_FLUSH_MASK 0x00000004U -#define EUR_CR_BIF_CTRL_FLUSH_SHIFT 2 -#define EUR_CR_BIF_CTRL_INVALDC_MASK 0x00000008U -#define EUR_CR_BIF_CTRL_INVALDC_SHIFT 3 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_MASK 0x00000100U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_SHIFT 8 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 -/* Register EUR_CR_BIF_INT_STAT */ -#define EUR_CR_BIF_INT_STAT 0x0C04 -#define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU -#define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0 -#define EUR_CR_BIF_INT_STAT_PF_N_RW_MASK 0x00004000U -#define EUR_CR_BIF_INT_STAT_PF_N_RW_SHIFT 14 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15 -/* Register EUR_CR_BIF_FAULT */ -#define EUR_CR_BIF_FAULT 0x0C08 -#define EUR_CR_BIF_FAULT_ADDR_MASK 0x0FFFF000U -#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ -#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_TA_REQ_BASE */ -#define EUR_CR_BIF_TA_REQ_BASE 0x0C90 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_MEM_REQ_STAT */ -#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 -/* Register EUR_CR_BIF_3D_REQ_BASE */ -#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_ZLS_REQ_BASE */ -#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 -/* Table EUR_CR_USE_CODE_BASE */ -/* Register EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) -#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x000FFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_MASK 0x00300000U -#define EUR_CR_USE_CODE_BASE_DM_SHIFT 20 -/* Number of entries in table EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 -#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 - -#endif /* _SGX520DEFS_KM_H_ */ - diff --git a/pvr-source/services4/srvkm/hwdefs/sgx530defs.h b/pvr-source/services4/srvkm/hwdefs/sgx530defs.h deleted file mode 100755 index 3223feb..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgx530defs.h +++ /dev/null @@ -1,542 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for SGX530. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGX530DEFS_KM_H_ -#define _SGX530DEFS_KM_H_ - -/* Register EUR_CR_CLKGATECTL */ -#define EUR_CR_CLKGATECTL 0x0000 -#define EUR_CR_CLKGATECTL_2D_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL_2D_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL_USE_CLKG_MASK 0x00300000U -#define EUR_CR_CLKGATECTL_USE_CLKG_SHIFT 20 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 -/* Register EUR_CR_CLKGATESTATUS */ -#define EUR_CR_CLKGATESTATUS 0x0004 -#define EUR_CR_CLKGATESTATUS_2D_CLKS_MASK 0x00000001U -#define EUR_CR_CLKGATESTATUS_2D_CLKS_SHIFT 0 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000010U -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 4 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000100U -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 8 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00001000U -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 12 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00010000U -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 16 -#define EUR_CR_CLKGATESTATUS_USE_CLKS_MASK 0x00100000U -#define EUR_CR_CLKGATESTATUS_USE_CLKS_SHIFT 20 -/* Register EUR_CR_CLKGATECTLOVR */ -#define EUR_CR_CLKGATECTLOVR 0x0008 -#define EUR_CR_CLKGATECTLOVR_2D_CLKO_MASK 0x00000003U -#define EUR_CR_CLKGATECTLOVR_2D_CLKO_SHIFT 0 -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000030U -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 4 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000300U -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 8 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x00003000U -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 12 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00030000U -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 16 -#define EUR_CR_CLKGATECTLOVR_USE_CLKO_MASK 0x00300000U -#define EUR_CR_CLKGATECTLOVR_USE_CLKO_SHIFT 20 -/* Register EUR_CR_CORE_ID */ -#define EUR_CR_CORE_ID 0x0010 -#define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU -#define EUR_CR_CORE_ID_CONFIG_SHIFT 0 -#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U -#define EUR_CR_CORE_ID_ID_SHIFT 16 -/* Register EUR_CR_CORE_REVISION */ -#define EUR_CR_CORE_REVISION 0x0014 -#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU -#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 -#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U -#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8 -#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U -#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 -#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U -#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 -/* Register EUR_CR_DESIGNER_REV_FIELD1 */ -#define EUR_CR_DESIGNER_REV_FIELD1 0x0018 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 -/* Register EUR_CR_DESIGNER_REV_FIELD2 */ -#define EUR_CR_DESIGNER_REV_FIELD2 0x001C -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 -/* Register EUR_CR_SOFT_RESET */ -#define EUR_CR_SOFT_RESET 0x0080 -#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U -#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 -#define EUR_CR_SOFT_RESET_TWOD_RESET_MASK 0x00000002U -#define EUR_CR_SOFT_RESET_TWOD_RESET_SHIFT 1 -#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U -#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 -#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00000008U -#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 3 -#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00000010U -#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 4 -#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U -#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5 -#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000040U -#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 6 -/* Register EUR_CR_EVENT_HOST_ENABLE2 */ -#define EUR_CR_EVENT_HOST_ENABLE2 0x0110 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_CLEAR2 */ -#define EUR_CR_EVENT_HOST_CLEAR2 0x0114 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_STATUS2 */ -#define EUR_CR_EVENT_STATUS2 0x0118 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_STATUS */ -#define EUR_CR_EVENT_STATUS 0x012CU -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_STATUS_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_STATUS_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_ENABLE */ -#define EUR_CR_EVENT_HOST_ENABLE 0x0130 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_CLEAR */ -#define EUR_CR_EVENT_HOST_CLEAR 0x0134 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_PDS_EXEC_BASE */ -#define EUR_CR_PDS_EXEC_BASE 0x0AB8 -#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_EVENT_KICKER */ -#define EUR_CR_EVENT_KICKER 0x0AC4 -#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0x0FFFFFF0U -#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 -/* Register EUR_CR_EVENT_KICK */ -#define EUR_CR_EVENT_KICK 0x0AC8 -#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK_NOW_SHIFT 0 -/* Register EUR_CR_EVENT_TIMER */ -#define EUR_CR_EVENT_TIMER 0x0ACC -#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U -#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 -#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU -#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 -/* Register EUR_CR_PDS_INV0 */ -#define EUR_CR_PDS_INV0 0x0AD0 -#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV0_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV1 */ -#define EUR_CR_PDS_INV1 0x0AD4 -#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV1_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV2 */ -#define EUR_CR_PDS_INV2 0x0AD8 -#define EUR_CR_PDS_INV2_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV2_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV3 */ -#define EUR_CR_PDS_INV3 0x0ADC -#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV3_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV_CSC */ -#define EUR_CR_PDS_INV_CSC 0x0AE0 -#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U -#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 -/* Register EUR_CR_PDS_PC_BASE */ -#define EUR_CR_PDS_PC_BASE 0x0B2C -#define EUR_CR_PDS_PC_BASE_ADDRESS_MASK 0x3FFFFFFFU -#define EUR_CR_PDS_PC_BASE_ADDRESS_SHIFT 0 -/* Register EUR_CR_BIF_CTRL */ -#define EUR_CR_BIF_CTRL 0x0C00 -#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U -#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 -#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U -#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1 -#define EUR_CR_BIF_CTRL_FLUSH_MASK 0x00000004U -#define EUR_CR_BIF_CTRL_FLUSH_SHIFT 2 -#define EUR_CR_BIF_CTRL_INVALDC_MASK 0x00000008U -#define EUR_CR_BIF_CTRL_INVALDC_SHIFT 3 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_MASK 0x00000100U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_SHIFT 8 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TWOD_MASK 0x00000800U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TWOD_SHIFT 11 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 -/* Register EUR_CR_BIF_INT_STAT */ -#define EUR_CR_BIF_INT_STAT 0x0C04 -#define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU -#define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0 -#define EUR_CR_BIF_INT_STAT_PF_N_RW_MASK 0x00004000U -#define EUR_CR_BIF_INT_STAT_PF_N_RW_SHIFT 14 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15 -/* Register EUR_CR_BIF_FAULT */ -#define EUR_CR_BIF_FAULT 0x0C08 -#define EUR_CR_BIF_FAULT_ADDR_MASK 0x0FFFF000U -#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ -#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_TWOD_REQ_BASE */ -#define EUR_CR_BIF_TWOD_REQ_BASE 0x0C88 -#define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_TA_REQ_BASE */ -#define EUR_CR_BIF_TA_REQ_BASE 0x0C90 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_MEM_REQ_STAT */ -#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 -/* Register EUR_CR_BIF_3D_REQ_BASE */ -#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_ZLS_REQ_BASE */ -#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_2D_BLIT_STATUS */ -#define EUR_CR_2D_BLIT_STATUS 0x0E04 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 -#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U -#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 -/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ -#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 -/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ -#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 -/* Table EUR_CR_USE_CODE_BASE */ -/* Register EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) -#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x00FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_MASK 0x03000000U -#define EUR_CR_USE_CODE_BASE_DM_SHIFT 24 -/* Number of entries in table EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 -#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 -#define EUR_CR_MNE_CR_CTRL 0x0D00 -#define EUR_CR_MNE_CR_CTRL_BYP_CC_N_MASK 0x00010000U -#define EUR_CR_MNE_CR_CTRL_BYP_CC_N_SHIFT 16 -#define EUR_CR_MNE_CR_CTRL_BYP_CC_MASK 0x00008000U -#define EUR_CR_MNE_CR_CTRL_BYP_CC_SHIFT 15 -#define EUR_CR_MNE_CR_CTRL_USE_INVAL_ADDR_MASK 0x00007800U -#define EUR_CR_MNE_CR_CTRL_USE_INVAL_ADDR_SHIFT 11 -#define EUR_CR_MNE_CR_CTRL_BYPASS_ALL_MASK 0x00000400U -#define EUR_CR_MNE_CR_CTRL_BYPASS_ALL_SHIFT 10 -#define EUR_CR_MNE_CR_CTRL_BYPASS_MASK 0x000003E0U -#define EUR_CR_MNE_CR_CTRL_BYPASS_SHIFT 5 -#define EUR_CR_MNE_CR_CTRL_PAUSE_MASK 0x00000010U -#define EUR_CR_MNE_CR_CTRL_PAUSE_SHIFT 4 -#define EUR_CR_MNE_CR_CTRL_INVAL_PREQ_MASK 0x0000000EU -#define EUR_CR_MNE_CR_CTRL_INVAL_PREQ_SHIFT 1 -#define EUR_CR_MNE_CR_CTRL_INVAL_PREQ_PDS_MASK (1UL<<EUR_CR_MNE_CR_CTRL_INVAL_PREQ_SHIFT+2) -#define EUR_CR_MNE_CR_CTRL_INVAL_PREQ_USEC_MASK (1UL<<EUR_CR_MNE_CR_CTRL_INVAL_PREQ_SHIFT+1) -#define EUR_CR_MNE_CR_CTRL_INVAL_PREQ_CACHE_MASK (1UL<<EUR_CR_MNE_CR_CTRL_INVAL_PREQ_SHIFT) -#define EUR_CR_MNE_CR_CTRL_INVAL_ALL_MASK 0x00000001U -#define EUR_CR_MNE_CR_CTRL_INVAL_ALL_SHIFT 0 -#define EUR_CR_MNE_CR_USE_INVAL 0x0D04 -#define EUR_CR_MNE_CR_USE_INVAL_ADDR_MASK 0xFFFFFFFFU -#define EUR_CR_MNE_CR_USE_INVAL_ADDR_SHIFT 0 -#define EUR_CR_MNE_CR_STAT 0x0D08 -#define EUR_CR_MNE_CR_STAT_PAUSED_MASK 0x00000400U -#define EUR_CR_MNE_CR_STAT_PAUSED_SHIFT 10 -#define EUR_CR_MNE_CR_STAT_READS_MASK 0x000003FFU -#define EUR_CR_MNE_CR_STAT_READS_SHIFT 0 -#define EUR_CR_MNE_CR_STAT_STATS 0x0D0C -#define EUR_CR_MNE_CR_STAT_STATS_RST_MASK 0x000FFFF0U -#define EUR_CR_MNE_CR_STAT_STATS_RST_SHIFT 4 -#define EUR_CR_MNE_CR_STAT_STATS_SEL_MASK 0x0000000FU -#define EUR_CR_MNE_CR_STAT_STATS_SEL_SHIFT 0 -#define EUR_CR_MNE_CR_STAT_STATS_OUT 0x0D10 -#define EUR_CR_MNE_CR_STAT_STATS_OUT_VALUE_MASK 0xFFFFFFFFU -#define EUR_CR_MNE_CR_STAT_STATS_OUT_VALUE_SHIFT 0 -#define EUR_CR_MNE_CR_EVENT_STATUS 0x0D14 -#define EUR_CR_MNE_CR_EVENT_STATUS_INVAL_MASK 0x00000001U -#define EUR_CR_MNE_CR_EVENT_STATUS_INVAL_SHIFT 0 -#define EUR_CR_MNE_CR_EVENT_CLEAR 0x0D18 -#define EUR_CR_MNE_CR_EVENT_CLEAR_INVAL_MASK 0x00000001U -#define EUR_CR_MNE_CR_EVENT_CLEAR_INVAL_SHIFT 0 -#define EUR_CR_MNE_CR_CTRL_INVAL 0x0D20 - -#endif /* _SGX530DEFS_KM_H_ */ - diff --git a/pvr-source/services4/srvkm/hwdefs/sgx531defs.h b/pvr-source/services4/srvkm/hwdefs/sgx531defs.h deleted file mode 100755 index 3295d89..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgx531defs.h +++ /dev/null @@ -1,601 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for SGX531. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGX531DEFS_KM_H_ -#define _SGX531DEFS_KM_H_ - -/* Register EUR_CR_CLKGATECTL */ -#define EUR_CR_CLKGATECTL 0x0000 -#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28 -/* Register EUR_CR_CLKGATECTL2 */ -#define EUR_CR_CLKGATECTL2 0x0004 -#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL2_MADD0_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL2_MADD0_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL2_MADD1_CLKG_MASK 0x00300000U -#define EUR_CR_CLKGATECTL2_MADD1_CLKG_SHIFT 20 -/* Register EUR_CR_CLKGATESTATUS */ -#define EUR_CR_CLKGATESTATUS 0x0008 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0 -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2 -#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U -#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3 -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5 -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6 -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7 -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8 -#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_MASK 0x00000200U -#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_SHIFT 9 -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10 -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11 -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12 -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13 -#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_MASK 0x00004000U -#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_SHIFT 14 -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15 -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16 -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17 -#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_MASK 0x00040000U -#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_SHIFT 18 -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20 -/* Register EUR_CR_CLKGATECTLOVR */ -#define EUR_CR_CLKGATECTLOVR 0x000C -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4 -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6 -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10 -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12 -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14 -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18 -/* Register EUR_CR_CORE_ID */ -#define EUR_CR_CORE_ID 0x0020 -#define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU -#define EUR_CR_CORE_ID_CONFIG_SHIFT 0 -#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U -#define EUR_CR_CORE_ID_ID_SHIFT 16 -/* Register EUR_CR_CORE_REVISION */ -#define EUR_CR_CORE_REVISION 0x0024 -#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU -#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 -#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U -#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8 -#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U -#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 -#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U -#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 -/* Register EUR_CR_DESIGNER_REV_FIELD1 */ -#define EUR_CR_DESIGNER_REV_FIELD1 0x0028 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 -/* Register EUR_CR_DESIGNER_REV_FIELD2 */ -#define EUR_CR_DESIGNER_REV_FIELD2 0x002C -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 -/* Register EUR_CR_SOFT_RESET */ -#define EUR_CR_SOFT_RESET 0x0080 -#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U -#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 -#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U -#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1 -#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U -#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 -#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U -#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3 -#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U -#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4 -#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U -#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5 -#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U -#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6 -#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U -#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7 -#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U -#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8 -#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U -#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9 -#define EUR_CR_SOFT_RESET_CACHEL2_RESET_MASK 0x00000400U -#define EUR_CR_SOFT_RESET_CACHEL2_RESET_SHIFT 10 -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11 -#define EUR_CR_SOFT_RESET_MADD_RESET_MASK 0x00001000U -#define EUR_CR_SOFT_RESET_MADD_RESET_SHIFT 12 -#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U -#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13 -#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U -#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14 -#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U -#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15 -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16 -#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U -#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17 -/* Register EUR_CR_EVENT_HOST_ENABLE2 */ -#define EUR_CR_EVENT_HOST_ENABLE2 0x0110 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_CLEAR2 */ -#define EUR_CR_EVENT_HOST_CLEAR2 0x0114 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_STATUS2 */ -#define EUR_CR_EVENT_STATUS2 0x0118 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_STATUS */ -#define EUR_CR_EVENT_STATUS 0x012CU -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_STATUS_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_STATUS_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_ENABLE */ -#define EUR_CR_EVENT_HOST_ENABLE 0x0130 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_CLEAR */ -#define EUR_CR_EVENT_HOST_CLEAR 0x0134 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_TIMER */ -#define EUR_CR_TIMER 0x0144 -#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU -#define EUR_CR_TIMER_VALUE_SHIFT 0 -/* Register EUR_CR_EVENT_KICK1 */ -#define EUR_CR_EVENT_KICK1 0x0AB0 -#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU -#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 -/* Register EUR_CR_PDS_EXEC_BASE */ -#define EUR_CR_PDS_EXEC_BASE 0x0AB8 -#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_EVENT_KICK2 */ -#define EUR_CR_EVENT_KICK2 0x0AC0 -#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0 -/* Register EUR_CR_EVENT_KICKER */ -#define EUR_CR_EVENT_KICKER 0x0AC4 -#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0x0FFFFFF0U -#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 -/* Register EUR_CR_EVENT_KICK */ -#define EUR_CR_EVENT_KICK 0x0AC8 -#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK_NOW_SHIFT 0 -/* Register EUR_CR_EVENT_TIMER */ -#define EUR_CR_EVENT_TIMER 0x0ACC -#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U -#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 -#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU -#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 -/* Register EUR_CR_PDS_INV0 */ -#define EUR_CR_PDS_INV0 0x0AD0 -#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV0_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV1 */ -#define EUR_CR_PDS_INV1 0x0AD4 -#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV1_DSC_SHIFT 0 -/* Register EUR_CR_EVENT_KICK3 */ -#define EUR_CR_EVENT_KICK3 0x0AD8 -#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0 -/* Register EUR_CR_PDS_INV3 */ -#define EUR_CR_PDS_INV3 0x0ADC -#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV3_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV_CSC */ -#define EUR_CR_PDS_INV_CSC 0x0AE0 -#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U -#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 -/* Register EUR_CR_PDS_PC_BASE */ -#define EUR_CR_PDS_PC_BASE 0x0B2C -#define EUR_CR_PDS_PC_BASE_ADDRESS_MASK 0x00FFFFFFU -#define EUR_CR_PDS_PC_BASE_ADDRESS_SHIFT 0 -/* Register EUR_CR_BIF_CTRL */ -#define EUR_CR_BIF_CTRL 0x0C00 -#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U -#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 -#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U -#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1 -#define EUR_CR_BIF_CTRL_FLUSH_MASK 0x00000004U -#define EUR_CR_BIF_CTRL_FLUSH_SHIFT 2 -#define EUR_CR_BIF_CTRL_INVALDC_MASK 0x00000008U -#define EUR_CR_BIF_CTRL_INVALDC_SHIFT 3 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_MASK 0x00000100U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_SHIFT 8 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 -/* Register EUR_CR_BIF_INT_STAT */ -#define EUR_CR_BIF_INT_STAT 0x0C04 -#define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU -#define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0 -#define EUR_CR_BIF_INT_STAT_PF_N_RW_MASK 0x00004000U -#define EUR_CR_BIF_INT_STAT_PF_N_RW_SHIFT 14 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15 -/* Register EUR_CR_BIF_FAULT */ -#define EUR_CR_BIF_FAULT 0x0C08 -#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U -#define EUR_CR_BIF_FAULT_SB_SHIFT 4 -#define EUR_CR_BIF_FAULT_ADDR_MASK 0x0FFFF000U -#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ -#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_TA_REQ_BASE */ -#define EUR_CR_BIF_TA_REQ_BASE 0x0C90 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_MEM_REQ_STAT */ -#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 -/* Register EUR_CR_BIF_3D_REQ_BASE */ -#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_ZLS_REQ_BASE */ -#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_2D_BLIT_STATUS */ -#define EUR_CR_2D_BLIT_STATUS 0x0E04 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 -#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U -#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 -/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ -#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 -/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ -#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 -/* Table EUR_CR_USE_CODE_BASE */ -/* Register EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) -#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x00FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_MASK 0x03000000U -#define EUR_CR_USE_CODE_BASE_DM_SHIFT 24 -/* Number of entries in table EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 -#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 - -#endif /* _SGX531DEFS_KM_H_ */ - diff --git a/pvr-source/services4/srvkm/hwdefs/sgx535defs.h b/pvr-source/services4/srvkm/hwdefs/sgx535defs.h deleted file mode 100755 index 8039da4..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgx535defs.h +++ /dev/null @@ -1,739 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for SGX535. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGX535DEFS_KM_H_ -#define _SGX535DEFS_KM_H_ - -/* Register EUR_CR_CLKGATECTL */ -#define EUR_CR_CLKGATECTL 0x0000 -#define EUR_CR_CLKGATECTL_2D_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL_2D_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL_USE_CLKG_MASK 0x00300000U -#define EUR_CR_CLKGATECTL_USE_CLKG_SHIFT 20 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 -/* Register EUR_CR_CLKGATESTATUS */ -#define EUR_CR_CLKGATESTATUS 0x0004 -#define EUR_CR_CLKGATESTATUS_2D_CLKS_MASK 0x00000001 -#define EUR_CR_CLKGATESTATUS_2D_CLKS_SHIFT 0 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000010U -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 4 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000100U -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 8 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00001000U -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 12 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00010000U -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 16 -#define EUR_CR_CLKGATESTATUS_USE_CLKS_MASK 0x00100000U -#define EUR_CR_CLKGATESTATUS_USE_CLKS_SHIFT 20 -/* Register EUR_CR_CLKGATECTLOVR */ -#define EUR_CR_CLKGATECTLOVR 0x0008 -#define EUR_CR_CLKGATECTLOVR_2D_CLKO_MASK 0x00000003U -#define EUR_CR_CLKGATECTLOVR_2D_CLKO_SHIFT 0 -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000030U -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 4 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000300U -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 8 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x00003000U -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 12 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00030000U -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 16 -#define EUR_CR_CLKGATECTLOVR_USE_CLKO_MASK 0x00300000U -#define EUR_CR_CLKGATECTLOVR_USE_CLKO_SHIFT 20 -/* Register EUR_CR_CORE_ID */ -#define EUR_CR_CORE_ID 0x0010 -#define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU -#define EUR_CR_CORE_ID_CONFIG_SHIFT 0 -#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U -#define EUR_CR_CORE_ID_ID_SHIFT 16 -/* Register EUR_CR_CORE_REVISION */ -#define EUR_CR_CORE_REVISION 0x0014 -#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU -#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 -#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U -#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8 -#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U -#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 -#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U -#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 -/* Register EUR_CR_DESIGNER_REV_FIELD1 */ -#define EUR_CR_DESIGNER_REV_FIELD1 0x0018 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 -/* Register EUR_CR_DESIGNER_REV_FIELD2 */ -#define EUR_CR_DESIGNER_REV_FIELD2 0x001C -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 -/* Register EUR_CR_SOFT_RESET */ -#define EUR_CR_SOFT_RESET 0x0080 -#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U -#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 -#define EUR_CR_SOFT_RESET_TWOD_RESET_MASK 0x00000002U -#define EUR_CR_SOFT_RESET_TWOD_RESET_SHIFT 1 -#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U -#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 -#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00000008U -#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 3 -#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00000010U -#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 4 -#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U -#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5 -#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000040U -#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 6 -/* Register EUR_CR_EVENT_HOST_ENABLE2 */ -#define EUR_CR_EVENT_HOST_ENABLE2 0x0110 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE2_BIF_REQUESTER_FAULT_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE2_BIF_REQUESTER_FAULT_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_CLEAR2 */ -#define EUR_CR_EVENT_HOST_CLEAR2 0x0114 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR2_BIF_REQUESTER_FAULT_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR2_BIF_REQUESTER_FAULT_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_STATUS2 */ -#define EUR_CR_EVENT_STATUS2 0x0118U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 7 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 6 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 5 -#define EUR_CR_EVENT_STATUS2_BIF_REQUESTER_FAULT_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS2_BIF_REQUESTER_FAULT_SHIFT 4 -#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_SHIFT 3 -#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_SHIFT 2 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_STATUS */ -#define EUR_CR_EVENT_STATUS 0x012CU -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_STATUS_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_STATUS_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_ENABLE */ -#define EUR_CR_EVENT_HOST_ENABLE 0x0130 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_CLEAR */ -#define EUR_CR_EVENT_HOST_CLEAR 0x0134 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_PDS_EXEC_BASE */ -#define EUR_CR_PDS_EXEC_BASE 0x0AB8 -#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_EVENT_KICKER */ -#define EUR_CR_EVENT_KICKER 0x0AC4 -#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 -/* Register EUR_CR_EVENT_KICK */ -#define EUR_CR_EVENT_KICK 0x0AC8 -#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK_NOW_SHIFT 0 -/* Register EUR_CR_EVENT_TIMER */ -#define EUR_CR_EVENT_TIMER 0x0ACC -#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U -#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 -#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU -#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 -/* Register EUR_CR_PDS_INV0 */ -#define EUR_CR_PDS_INV0 0x0AD0 -#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV0_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV1 */ -#define EUR_CR_PDS_INV1 0x0AD4 -#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV1_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV2 */ -#define EUR_CR_PDS_INV2 0x0AD8 -#define EUR_CR_PDS_INV2_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV2_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV3 */ -#define EUR_CR_PDS_INV3 0x0ADC -#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV3_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV_CSC */ -#define EUR_CR_PDS_INV_CSC 0x0AE0 -#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U -#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 -/* Register EUR_CR_PDS_PC_BASE */ -#define EUR_CR_PDS_PC_BASE 0x0B2C -#define EUR_CR_PDS_PC_BASE_ADDRESS_MASK 0x3FFFFFFFU -#define EUR_CR_PDS_PC_BASE_ADDRESS_SHIFT 0 -/* Register EUR_CR_BIF_CTRL */ -#define EUR_CR_BIF_CTRL 0x0C00 -#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U -#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 -#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U -#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1 -#define EUR_CR_BIF_CTRL_FLUSH_MASK 0x00000004U -#define EUR_CR_BIF_CTRL_FLUSH_SHIFT 2 -#define EUR_CR_BIF_CTRL_INVALDC_MASK 0x00000008U -#define EUR_CR_BIF_CTRL_INVALDC_SHIFT 3 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_MASK 0x00000100U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_SHIFT 8 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TWOD_MASK 0x00000800U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TWOD_SHIFT 11 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_MASK 0x00010000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_SHIFT 16 -/* Register EUR_CR_BIF_INT_STAT */ -#define EUR_CR_BIF_INT_STAT 0x0C04 -#define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU -#define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0 -#define EUR_CR_BIF_INT_STAT_PF_N_RW_MASK 0x00004000U -#define EUR_CR_BIF_INT_STAT_PF_N_RW_SHIFT 14 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15 -/* Register EUR_CR_BIF_FAULT */ -#define EUR_CR_BIF_FAULT 0x0C08 -#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_TILE0 */ -#define EUR_CR_BIF_TILE0 0x0C0C -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE0_CFG_SHIFT 24 -/* Register EUR_CR_BIF_TILE1 */ -#define EUR_CR_BIF_TILE1 0x0C10 -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE1_CFG_SHIFT 24 -/* Register EUR_CR_BIF_TILE2 */ -#define EUR_CR_BIF_TILE2 0x0C14 -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE2_CFG_SHIFT 24 -/* Register EUR_CR_BIF_TILE3 */ -#define EUR_CR_BIF_TILE3 0x0C18 -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE3_CFG_SHIFT 24 -/* Register EUR_CR_BIF_TILE4 */ -#define EUR_CR_BIF_TILE4 0x0C1C -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE4_CFG_SHIFT 24 -/* Register EUR_CR_BIF_TILE5 */ -#define EUR_CR_BIF_TILE5 0x0C20 -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE5_CFG_SHIFT 24 -/* Register EUR_CR_BIF_TILE6 */ -#define EUR_CR_BIF_TILE6 0x0C24 -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE6_CFG_SHIFT 24 -/* Register EUR_CR_BIF_TILE7 */ -#define EUR_CR_BIF_TILE7 0x0C28 -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE7_CFG_SHIFT 24 -/* Register EUR_CR_BIF_TILE8 */ -#define EUR_CR_BIF_TILE8 0x0C2C -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE8_CFG_SHIFT 24 -/* Register EUR_CR_BIF_TILE9 */ -#define EUR_CR_BIF_TILE9 0x0C30 -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE9_CFG_SHIFT 24 -/* Register EUR_CR_BIF_DIR_LIST_BASE1 */ -#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38 -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE2 */ -#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE3 */ -#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40 -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE4 */ -#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44 -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE5 */ -#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48 -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE6 */ -#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE7 */ -#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50 -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE8 */ -#define EUR_CR_BIF_DIR_LIST_BASE8 0x0C54 -#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE9 */ -#define EUR_CR_BIF_DIR_LIST_BASE9 0x0C58 -#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE10 */ -#define EUR_CR_BIF_DIR_LIST_BASE10 0x0C5C -#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE11 */ -#define EUR_CR_BIF_DIR_LIST_BASE11 0x0C60 -#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE12 */ -#define EUR_CR_BIF_DIR_LIST_BASE12 0x0C64 -#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE13 */ -#define EUR_CR_BIF_DIR_LIST_BASE13 0x0C68 -#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE14 */ -#define EUR_CR_BIF_DIR_LIST_BASE14 0x0C6C -#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE15 */ -#define EUR_CR_BIF_DIR_LIST_BASE15 0x0C70 -#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_BANK_SET */ -#define EUR_CR_BIF_BANK_SET 0x0C74 -#define EUR_CR_BIF_BANK_SET_SELECT_MASK 0x000003FFU -#define EUR_CR_BIF_BANK_SET_SELECT_SHIFT 0 -/* Register EUR_CR_BIF_BANK0 */ -#define EUR_CR_BIF_BANK0 0x0C78 -#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK0_INDEX_HOST_MASK 0x00000F00U -#define EUR_CR_BIF_BANK0_INDEX_HOST_SHIFT 8 -#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK0_INDEX_2D_MASK 0x000F0000U -#define EUR_CR_BIF_BANK0_INDEX_2D_SHIFT 16 -/* Register EUR_CR_BIF_BANK1 */ -#define EUR_CR_BIF_BANK1 0x0C7C -#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK1_INDEX_HOST_MASK 0x00000F00U -#define EUR_CR_BIF_BANK1_INDEX_HOST_SHIFT 8 -#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK1_INDEX_2D_MASK 0x000F0000U -#define EUR_CR_BIF_BANK1_INDEX_2D_SHIFT 16 -/* Register EUR_CR_BIF_ADT_TTE */ -#define EUR_CR_BIF_ADT_TTE 0x0C80 -#define EUR_CR_BIF_ADT_TTE_VALUE_MASK 0x000000FFU -#define EUR_CR_BIF_ADT_TTE_VALUE_SHIFT 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ -#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_TWOD_REQ_BASE */ -#define EUR_CR_BIF_TWOD_REQ_BASE 0x0C88 -#define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_TA_REQ_BASE */ -#define EUR_CR_BIF_TA_REQ_BASE 0x0C90 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_MEM_ARB_FLOWRATES_1 */ -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1 0x0C94 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_MMU_MASK 0x00000007U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_MMU_SHIFT 0 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_CACHE_MASK 0x00000038U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_CACHE_SHIFT 3 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_VDM_MASK 0x000001C0U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_VDM_SHIFT 6 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TE_MASK 0x00000E00U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TE_SHIFT 9 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TWOD_MASK 0x00007000U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TWOD_SHIFT 12 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_PBE_MASK 0x00038000U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_PBE_SHIFT 15 -/* Register EUR_CR_BIF_MEM_ARB_FLOWRATES_2 */ -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2 0x0C98 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_HOST_MASK 0x00000007U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_HOST_SHIFT 0 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_USE_MASK 0x00000038U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_USE_SHIFT 3 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_ISP_MASK 0x000001C0U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_ISP_SHIFT 6 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_TSPP_MASK 0x00000E00U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_TSPP_SHIFT 9 -/* Register EUR_CR_BIF_MEM_ARB_CONFIG */ -#define EUR_CR_BIF_MEM_ARB_CONFIG 0x0CA0 -#define EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_MASK 0x0000000FU -#define EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_SHIFT 0 -#define EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_MASK 0x00000FF0U -#define EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_SHIFT 4 -#define EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_MASK 0x00FFF000U -#define EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_SHIFT 12 -/* Register EUR_CR_BIF_MEM_REQ_STAT */ -#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 -/* Register EUR_CR_BIF_3D_REQ_BASE */ -#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_ZLS_REQ_BASE */ -#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_BANK_STATUS */ -#define EUR_CR_BIF_BANK_STATUS 0x0CB4 -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0 -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 -/* Register EUR_CR_2D_BLIT_STATUS */ -#define EUR_CR_2D_BLIT_STATUS 0x0E04 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 -#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U -#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 -/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ -#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 -/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ -#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 -/* Register EUR_CR_2D_SOCIF */ -#define EUR_CR_2D_SOCIF 0x0E18 -#define EUR_CR_2D_SOCIF_FREESPACE_MASK 0x000000FFU -#define EUR_CR_2D_SOCIF_FREESPACE_SHIFT 0 -/* Register EUR_CR_2D_ALPHA */ -#define EUR_CR_2D_ALPHA 0x0E1C -#define EUR_CR_2D_ALPHA_COMPONENT_ONE_MASK 0x0000FF00U -#define EUR_CR_2D_ALPHA_COMPONENT_ONE_SHIFT 8 -#define EUR_CR_2D_ALPHA_COMPONENT_ZERO_MASK 0x000000FFU -#define EUR_CR_2D_ALPHA_COMPONENT_ZERO_SHIFT 0 -/* Table EUR_CR_USE_CODE_BASE */ -/* Register EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) -#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_SHIFT 25 -/* Number of entries in table EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 -#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 - -#endif /* _SGX535DEFS_KM_H_ */ - diff --git a/pvr-source/services4/srvkm/hwdefs/sgx540defs.h b/pvr-source/services4/srvkm/hwdefs/sgx540defs.h deleted file mode 100755 index 47080c7..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgx540defs.h +++ /dev/null @@ -1,605 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for SGX540. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGX540DEFS_KM_H_ -#define _SGX540DEFS_KM_H_ - -/* Register EUR_CR_CLKGATECTL */ -#define EUR_CR_CLKGATECTL 0x0000 -#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28 -/* Register EUR_CR_CLKGATECTL2 */ -#define EUR_CR_CLKGATECTL2 0x0004 -#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL2_MADD0_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL2_MADD0_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL2_MADD1_CLKG_MASK 0x00300000U -#define EUR_CR_CLKGATECTL2_MADD1_CLKG_SHIFT 20 -/* Register EUR_CR_CLKGATESTATUS */ -#define EUR_CR_CLKGATESTATUS 0x0008 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0 -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2 -#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U -#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3 -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5 -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6 -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7 -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8 -#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_MASK 0x00000200U -#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_SHIFT 9 -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10 -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11 -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12 -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13 -#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_MASK 0x00004000U -#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_SHIFT 14 -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15 -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16 -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17 -#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_MASK 0x00040000U -#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_SHIFT 18 -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20 -/* Register EUR_CR_CLKGATECTLOVR */ -#define EUR_CR_CLKGATECTLOVR 0x000C -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4 -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6 -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10 -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12 -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14 -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18 -/* Register EUR_CR_POWER */ -#define EUR_CR_POWER 0x001C -#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U -#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0 -/* Register EUR_CR_CORE_ID */ -#define EUR_CR_CORE_ID 0x0020 -#define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU -#define EUR_CR_CORE_ID_CONFIG_SHIFT 0 -#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U -#define EUR_CR_CORE_ID_ID_SHIFT 16 -/* Register EUR_CR_CORE_REVISION */ -#define EUR_CR_CORE_REVISION 0x0024 -#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU -#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 -#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U -#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8 -#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U -#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 -#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U -#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 -/* Register EUR_CR_DESIGNER_REV_FIELD1 */ -#define EUR_CR_DESIGNER_REV_FIELD1 0x0028 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 -/* Register EUR_CR_DESIGNER_REV_FIELD2 */ -#define EUR_CR_DESIGNER_REV_FIELD2 0x002C -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 -/* Register EUR_CR_SOFT_RESET */ -#define EUR_CR_SOFT_RESET 0x0080 -#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U -#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 -#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U -#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1 -#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U -#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 -#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U -#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3 -#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U -#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4 -#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U -#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5 -#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U -#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6 -#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U -#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7 -#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U -#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8 -#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U -#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9 -#define EUR_CR_SOFT_RESET_CACHEL2_RESET_MASK 0x00000400U -#define EUR_CR_SOFT_RESET_CACHEL2_RESET_SHIFT 10 -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11 -#define EUR_CR_SOFT_RESET_MADD_RESET_MASK 0x00001000U -#define EUR_CR_SOFT_RESET_MADD_RESET_SHIFT 12 -#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U -#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13 -#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U -#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14 -#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U -#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15 -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16 -#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U -#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17 -/* Register EUR_CR_EVENT_HOST_ENABLE2 */ -#define EUR_CR_EVENT_HOST_ENABLE2 0x0110 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_CLEAR2 */ -#define EUR_CR_EVENT_HOST_CLEAR2 0x0114 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_STATUS2 */ -#define EUR_CR_EVENT_STATUS2 0x0118 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 -/* Register EUR_CR_EVENT_STATUS */ -#define EUR_CR_EVENT_STATUS 0x012CU -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_STATUS_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_STATUS_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_ENABLE */ -#define EUR_CR_EVENT_HOST_ENABLE 0x0130 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_EVENT_HOST_CLEAR */ -#define EUR_CR_EVENT_HOST_CLEAR 0x0134 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_SHIFT 27 -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_MASK 0x00020000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_SHIFT 17 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 -/* Register EUR_CR_TIMER */ -#define EUR_CR_TIMER 0x0144 -#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU -#define EUR_CR_TIMER_VALUE_SHIFT 0 -/* Register EUR_CR_EVENT_KICK1 */ -#define EUR_CR_EVENT_KICK1 0x0AB0 -#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU -#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 -/* Register EUR_CR_PDS_EXEC_BASE */ -#define EUR_CR_PDS_EXEC_BASE 0x0AB8 -#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_EVENT_KICK2 */ -#define EUR_CR_EVENT_KICK2 0x0AC0 -#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0 -/* Register EUR_CR_EVENT_KICKER */ -#define EUR_CR_EVENT_KICKER 0x0AC4 -#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0x0FFFFFF0U -#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 -/* Register EUR_CR_EVENT_KICK */ -#define EUR_CR_EVENT_KICK 0x0AC8 -#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK_NOW_SHIFT 0 -/* Register EUR_CR_EVENT_TIMER */ -#define EUR_CR_EVENT_TIMER 0x0ACC -#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U -#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 -#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU -#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 -/* Register EUR_CR_PDS_INV0 */ -#define EUR_CR_PDS_INV0 0x0AD0 -#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV0_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV1 */ -#define EUR_CR_PDS_INV1 0x0AD4 -#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV1_DSC_SHIFT 0 -/* Register EUR_CR_EVENT_KICK3 */ -#define EUR_CR_EVENT_KICK3 0x0AD8 -#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0 -/* Register EUR_CR_PDS_INV3 */ -#define EUR_CR_PDS_INV3 0x0ADC -#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV3_DSC_SHIFT 0 -/* Register EUR_CR_PDS_INV_CSC */ -#define EUR_CR_PDS_INV_CSC 0x0AE0 -#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U -#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 -/* Register EUR_CR_PDS_PC_BASE */ -#define EUR_CR_PDS_PC_BASE 0x0B2C -#define EUR_CR_PDS_PC_BASE_ADDRESS_MASK 0x00FFFFFFU -#define EUR_CR_PDS_PC_BASE_ADDRESS_SHIFT 0 -/* Register EUR_CR_BIF_CTRL */ -#define EUR_CR_BIF_CTRL 0x0C00 -#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U -#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 -#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U -#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1 -#define EUR_CR_BIF_CTRL_FLUSH_MASK 0x00000004U -#define EUR_CR_BIF_CTRL_FLUSH_SHIFT 2 -#define EUR_CR_BIF_CTRL_INVALDC_MASK 0x00000008U -#define EUR_CR_BIF_CTRL_INVALDC_SHIFT 3 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_MASK 0x00000100U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_SHIFT 8 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 -/* Register EUR_CR_BIF_INT_STAT */ -#define EUR_CR_BIF_INT_STAT 0x0C04 -#define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU -#define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0 -#define EUR_CR_BIF_INT_STAT_PF_N_RW_MASK 0x00004000U -#define EUR_CR_BIF_INT_STAT_PF_N_RW_SHIFT 14 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15 -/* Register EUR_CR_BIF_FAULT */ -#define EUR_CR_BIF_FAULT 0x0C08 -#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U -#define EUR_CR_BIF_FAULT_SB_SHIFT 4 -#define EUR_CR_BIF_FAULT_ADDR_MASK 0x0FFFF000U -#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ -#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 -/* Register EUR_CR_BIF_TA_REQ_BASE */ -#define EUR_CR_BIF_TA_REQ_BASE 0x0C90 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_MEM_REQ_STAT */ -#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 -/* Register EUR_CR_BIF_3D_REQ_BASE */ -#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_BIF_ZLS_REQ_BASE */ -#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0x0FF00000U -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 -/* Register EUR_CR_2D_BLIT_STATUS */ -#define EUR_CR_2D_BLIT_STATUS 0x0E04 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 -#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U -#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 -/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ -#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 -/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ -#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 -/* Table EUR_CR_USE_CODE_BASE */ -/* Register EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) -#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x00FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_MASK 0x03000000U -#define EUR_CR_USE_CODE_BASE_DM_SHIFT 24 -/* Number of entries in table EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 -#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 - -#endif /* _SGX540DEFS_KM_H_ */ - diff --git a/pvr-source/services4/srvkm/hwdefs/sgx543_v1.164defs.h b/pvr-source/services4/srvkm/hwdefs/sgx543_v1.164defs.h deleted file mode 100755 index 8c8b353..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgx543_v1.164defs.h +++ /dev/null @@ -1,1396 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for SGX543_V1.164. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGX543_V1_164DEFS_KM_H_ -#define _SGX543_V1_164DEFS_KM_H_ - -/* Register EUR_CR_CLKGATECTL */ -#define EUR_CR_CLKGATECTL 0x0000 -#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL_ISP_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL_ISP2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL_TSP_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL_TE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL_MTE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL_DPM_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL_VDM_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL_PDS_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL_TA_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_MASK 0x00300000U -#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SHIFT 20 -#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0 -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28 -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SIGNED 0 -/* Register EUR_CR_CLKGATECTL2 */ -#define EUR_CR_CLKGATECTL2 0x0004 -#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL2_PBE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL2_USE0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL2_USE1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_MASK 0x00C00000U -#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SHIFT 22 -#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_MASK 0x03000000U -#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SHIFT 24 -#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_MASK 0x0C000000U -#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SHIFT 26 -#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SIGNED 0 -/* Register EUR_CR_CLKGATESTATUS */ -#define EUR_CR_CLKGATESTATUS 0x0008 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1 -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U -#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3 -#define EUR_CR_CLKGATESTATUS_TE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4 -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6 -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7 -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8 -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_MASK 0x00000200U -#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SHIFT 9 -#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10 -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11 -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12 -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13 -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15 -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16 -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17 -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19 -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_MASK 0x00200000U -#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SHIFT 21 -#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_MASK 0x00400000U -#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SHIFT 22 -#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_MASK 0x00800000U -#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SHIFT 23 -#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_MASK 0x01000000U -#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SHIFT 24 -#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SIGNED 0 -/* Register EUR_CR_CLKGATECTLOVR */ -#define EUR_CR_CLKGATECTLOVR 0x000C -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2 -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6 -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8 -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12 -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14 -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16 -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_MASK 0x00300000U -#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SHIFT 20 -#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SIGNED 0 -/* Register EUR_CR_POWER */ -#define EUR_CR_POWER 0x001C -#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U -#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0 -#define EUR_CR_POWER_PIPE_DISABLE_SIGNED 0 -/* Register EUR_CR_CORE_ID */ -#define EUR_CR_CORE_ID 0x0020 -#define EUR_CR_CORE_ID_CONFIG_MULTI_MASK 0x00000001U -#define EUR_CR_CORE_ID_CONFIG_MULTI_SHIFT 0 -#define EUR_CR_CORE_ID_CONFIG_MULTI_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_BASE_MASK 0x00000002U -#define EUR_CR_CORE_ID_CONFIG_BASE_SHIFT 1 -#define EUR_CR_CORE_ID_CONFIG_BASE_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_MASK 0x000000FCU -#define EUR_CR_CORE_ID_CONFIG_SHIFT 2 -#define EUR_CR_CORE_ID_CONFIG_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_CORES_MASK 0x00000F00U -#define EUR_CR_CORE_ID_CONFIG_CORES_SHIFT 8 -#define EUR_CR_CORE_ID_CONFIG_CORES_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_SLC_MASK 0x0000F000U -#define EUR_CR_CORE_ID_CONFIG_SLC_SHIFT 12 -#define EUR_CR_CORE_ID_CONFIG_SLC_SIGNED 0 -#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U -#define EUR_CR_CORE_ID_ID_SHIFT 16 -#define EUR_CR_CORE_ID_ID_SIGNED 0 -/* Register EUR_CR_CORE_REVISION */ -#define EUR_CR_CORE_REVISION 0x0024 -#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU -#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 -#define EUR_CR_CORE_REVISION_MAINTENANCE_SIGNED 0 -#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U -#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8 -#define EUR_CR_CORE_REVISION_MINOR_SIGNED 0 -#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U -#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 -#define EUR_CR_CORE_REVISION_MAJOR_SIGNED 0 -#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U -#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 -#define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0 -/* Register EUR_CR_DESIGNER_REV_FIELD1 */ -#define EUR_CR_DESIGNER_REV_FIELD1 0x0028 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0 -/* Register EUR_CR_DESIGNER_REV_FIELD2 */ -#define EUR_CR_DESIGNER_REV_FIELD2 0x002C -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0 -/* Register EUR_CR_SOFT_RESET */ -#define EUR_CR_SOFT_RESET 0x0080 -#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U -#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 -#define EUR_CR_SOFT_RESET_BIF_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U -#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1 -#define EUR_CR_SOFT_RESET_VDM_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U -#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 -#define EUR_CR_SOFT_RESET_DPM_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U -#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3 -#define EUR_CR_SOFT_RESET_TE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U -#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4 -#define EUR_CR_SOFT_RESET_MTE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U -#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5 -#define EUR_CR_SOFT_RESET_ISP_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U -#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6 -#define EUR_CR_SOFT_RESET_ISP2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U -#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7 -#define EUR_CR_SOFT_RESET_TSP_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U -#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8 -#define EUR_CR_SOFT_RESET_PDS_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U -#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9 -#define EUR_CR_SOFT_RESET_PBE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK 0x00000400U -#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SHIFT 10 -#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11 -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U -#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13 -#define EUR_CR_SOFT_RESET_ITR_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U -#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14 -#define EUR_CR_SOFT_RESET_TEX_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U -#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15 -#define EUR_CR_SOFT_RESET_USE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16 -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U -#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17 -#define EUR_CR_SOFT_RESET_TA_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK 0x00040000U -#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SHIFT 18 -#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK 0x00080000U -#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SHIFT 19 -#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_ENABLE2 */ -#define EUR_CR_EVENT_HOST_ENABLE2 0x0110 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_CLEAR2 */ -#define EUR_CR_EVENT_HOST_CLEAR2 0x0114 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_STATUS2 */ -#define EUR_CR_EVENT_STATUS2 0x0118 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SHIFT 9 -#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 -#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SHIFT 7 -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SHIFT 6 -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 -#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_STATUS */ -#define EUR_CR_EVENT_STATUS 0x012C -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 -#define EUR_CR_EVENT_STATUS_TIMER_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_STATUS_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_STATUS_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_ENABLE */ -#define EUR_CR_EVENT_HOST_ENABLE 0x0130 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_CLEAR */ -#define EUR_CR_EVENT_HOST_CLEAR 0x0134 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_TIMER */ -#define EUR_CR_TIMER 0x0144 -#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU -#define EUR_CR_TIMER_VALUE_SHIFT 0 -#define EUR_CR_TIMER_VALUE_SIGNED 0 -/* Register EUR_CR_EVENT_KICK1 */ -#define EUR_CR_EVENT_KICK1 0x0AB0 -#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU -#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK1_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_KICK2 */ -#define EUR_CR_EVENT_KICK2 0x0AC0 -#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK2_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_KICKER */ -#define EUR_CR_EVENT_KICKER 0x0AC4 -#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 -#define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0 -/* Register EUR_CR_EVENT_KICK */ -#define EUR_CR_EVENT_KICK 0x0AC8 -#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_TIMER */ -#define EUR_CR_EVENT_TIMER 0x0ACC -#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U -#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 -#define EUR_CR_EVENT_TIMER_ENABLE_SIGNED 0 -#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU -#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 -#define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0 -/* Register EUR_CR_PDS_INV0 */ -#define EUR_CR_PDS_INV0 0x0AD0 -#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV0_DSC_SHIFT 0 -#define EUR_CR_PDS_INV0_DSC_SIGNED 0 -/* Register EUR_CR_PDS_INV1 */ -#define EUR_CR_PDS_INV1 0x0AD4 -#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV1_DSC_SHIFT 0 -#define EUR_CR_PDS_INV1_DSC_SIGNED 0 -/* Register EUR_CR_EVENT_KICK3 */ -#define EUR_CR_EVENT_KICK3 0x0AD8 -#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK3_NOW_SIGNED 0 -/* Register EUR_CR_PDS_INV3 */ -#define EUR_CR_PDS_INV3 0x0ADC -#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV3_DSC_SHIFT 0 -#define EUR_CR_PDS_INV3_DSC_SIGNED 0 -/* Register EUR_CR_PDS_INV_CSC */ -#define EUR_CR_PDS_INV_CSC 0x0AE0 -#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U -#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 -#define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0 -/* Register EUR_CR_BIF_CTRL */ -#define EUR_CR_BIF_CTRL 0x0C00 -#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U -#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 -#define EUR_CR_BIF_CTRL_NOREORDER_SIGNED 0 -#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U -#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1 -#define EUR_CR_BIF_CTRL_PAUSE_SIGNED 0 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_MASK 0x00000400U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SHIFT 10 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_MASK 0x00010000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SHIFT 16 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_MASK 0x00020000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SHIFT 17 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_MASK 0x00040000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SHIFT 18 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0 -/* Register EUR_CR_BIF_INT_STAT */ -#define EUR_CR_BIF_INT_STAT 0x0C04 -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x00003FFFU -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0 -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SIGNED 0 -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK 0x00070000U -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SHIFT 16 -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SIGNED 0 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0 -/* Register EUR_CR_BIF_FAULT */ -#define EUR_CR_BIF_FAULT 0x0C08 -#define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU -#define EUR_CR_BIF_FAULT_CID_SHIFT 0 -#define EUR_CR_BIF_FAULT_CID_SIGNED 0 -#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U -#define EUR_CR_BIF_FAULT_SB_SHIFT 4 -#define EUR_CR_BIF_FAULT_SB_SIGNED 0 -#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 -#define EUR_CR_BIF_FAULT_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_TILE0 */ -#define EUR_CR_BIF_TILE0 0x0C0C -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE0_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE0_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE1 */ -#define EUR_CR_BIF_TILE1 0x0C10 -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE1_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE1_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE2 */ -#define EUR_CR_BIF_TILE2 0x0C14 -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE2_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE2_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE3 */ -#define EUR_CR_BIF_TILE3 0x0C18 -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE3_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE3_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE4 */ -#define EUR_CR_BIF_TILE4 0x0C1C -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE4_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE4_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE5 */ -#define EUR_CR_BIF_TILE5 0x0C20 -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE5_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE5_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE6 */ -#define EUR_CR_BIF_TILE6 0x0C24 -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE6_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE6_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE7 */ -#define EUR_CR_BIF_TILE7 0x0C28 -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE7_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE7_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE8 */ -#define EUR_CR_BIF_TILE8 0x0C2C -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE8_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE8_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE9 */ -#define EUR_CR_BIF_TILE9 0x0C30 -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE9_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE9_CFG_SIGNED 0 -/* Register EUR_CR_BIF_CTRL_INVAL */ -#define EUR_CR_BIF_CTRL_INVAL 0x0C34 -#define EUR_CR_BIF_CTRL_INVAL_PTE_MASK 0x00000004U -#define EUR_CR_BIF_CTRL_INVAL_PTE_SHIFT 2 -#define EUR_CR_BIF_CTRL_INVAL_PTE_SIGNED 0 -#define EUR_CR_BIF_CTRL_INVAL_ALL_MASK 0x00000008U -#define EUR_CR_BIF_CTRL_INVAL_ALL_SHIFT 3 -#define EUR_CR_BIF_CTRL_INVAL_ALL_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE1 */ -#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38 -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE2 */ -#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE3 */ -#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40 -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE4 */ -#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44 -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE5 */ -#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48 -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE6 */ -#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE7 */ -#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50 -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_BANK_SET */ -#define EUR_CR_BIF_BANK_SET 0x0C74 -#define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U -#define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0 -#define EUR_CR_BIF_BANK_SET_SELECT_2D_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_3D_MASK 0x0000000CU -#define EUR_CR_BIF_BANK_SET_SELECT_3D_SHIFT 2 -#define EUR_CR_BIF_BANK_SET_SELECT_3D_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_MASK 0x00000010U -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SHIFT 4 -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_TA_MASK 0x000000C0U -#define EUR_CR_BIF_BANK_SET_SELECT_TA_SHIFT 6 -#define EUR_CR_BIF_BANK_SET_SELECT_TA_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_MASK 0x00000100U -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SHIFT 8 -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9 -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0 -/* Register EUR_CR_BIF_BANK0 */ -#define EUR_CR_BIF_BANK0 0x0C78 -#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK0_INDEX_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK0_INDEX_TA_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK0_INDEX_3D_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_PTLA_MASK 0x000F0000U -#define EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT 16 -#define EUR_CR_BIF_BANK0_INDEX_PTLA_SIGNED 0 -/* Register EUR_CR_BIF_BANK1 */ -#define EUR_CR_BIF_BANK1 0x0C7C -#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK1_INDEX_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK1_INDEX_TA_SIGNED 0 -#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ -#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_TA_REQ_BASE */ -#define EUR_CR_BIF_TA_REQ_BASE 0x0C90 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_MEM_REQ_STAT */ -#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0 -/* Register EUR_CR_BIF_3D_REQ_BASE */ -#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_ZLS_REQ_BASE */ -#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_BANK_STATUS */ -#define EUR_CR_BIF_BANK_STATUS 0x0CB4 -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0 -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SIGNED 0 -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0 -/* Register EUR_CR_BIF_MMU_CTRL */ -#define EUR_CR_BIF_MMU_CTRL 0x0CD0 -#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U -#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0 -#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U -#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1 -#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_MASK 0x00000008U -#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SHIFT 3 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U -#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0 -/* Register EUR_CR_2D_BLIT_STATUS */ -#define EUR_CR_2D_BLIT_STATUS 0x0E04 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SIGNED 0 -#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U -#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 -#define EUR_CR_2D_BLIT_STATUS_BUSY_SIGNED 0 -/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ -#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SIGNED 0 -/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ -#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SIGNED 0 -/* Register EUR_CR_BREAKPOINT0_START */ -#define EUR_CR_BREAKPOINT0_START 0x0F44 -#define EUR_CR_BREAKPOINT0_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT0_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT0_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT0_END */ -#define EUR_CR_BREAKPOINT0_END 0x0F48 -#define EUR_CR_BREAKPOINT0_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT0_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT0_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT0 */ -#define EUR_CR_BREAKPOINT0 0x0F4C -#define EUR_CR_BREAKPOINT0_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT0_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT0_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT1_START */ -#define EUR_CR_BREAKPOINT1_START 0x0F50 -#define EUR_CR_BREAKPOINT1_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT1_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT1_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT1_END */ -#define EUR_CR_BREAKPOINT1_END 0x0F54 -#define EUR_CR_BREAKPOINT1_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT1_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT1_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT1 */ -#define EUR_CR_BREAKPOINT1 0x0F58 -#define EUR_CR_BREAKPOINT1_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT1_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT1_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT2_START */ -#define EUR_CR_BREAKPOINT2_START 0x0F5C -#define EUR_CR_BREAKPOINT2_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT2_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT2_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT2_END */ -#define EUR_CR_BREAKPOINT2_END 0x0F60 -#define EUR_CR_BREAKPOINT2_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT2_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT2_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT2 */ -#define EUR_CR_BREAKPOINT2 0x0F64 -#define EUR_CR_BREAKPOINT2_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT2_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT2_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT3_START */ -#define EUR_CR_BREAKPOINT3_START 0x0F68 -#define EUR_CR_BREAKPOINT3_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT3_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT3_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT3_END */ -#define EUR_CR_BREAKPOINT3_END 0x0F6C -#define EUR_CR_BREAKPOINT3_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT3_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT3_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT3 */ -#define EUR_CR_BREAKPOINT3 0x0F70 -#define EUR_CR_BREAKPOINT3_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT3_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT3_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT_READ */ -#define EUR_CR_BREAKPOINT_READ 0x0F74 -#define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT_TRAP */ -#define EUR_CR_BREAKPOINT_TRAP 0x0F78 -#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 -#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 -#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U -#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 -#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 -/* Register EUR_CR_BREAKPOINT */ -#define EUR_CR_BREAKPOINT 0x0F7C -#define EUR_CR_BREAKPOINT_MODULE_ID_MASK 0x000003C0U -#define EUR_CR_BREAKPOINT_MODULE_ID_SHIFT 6 -#define EUR_CR_BREAKPOINT_MODULE_ID_SIGNED 0 -#define EUR_CR_BREAKPOINT_ID_MASK 0x00000030U -#define EUR_CR_BREAKPOINT_ID_SHIFT 4 -#define EUR_CR_BREAKPOINT_ID_SIGNED 0 -#define EUR_CR_BREAKPOINT_UNTRAPPED_MASK 0x00000008U -#define EUR_CR_BREAKPOINT_UNTRAPPED_SHIFT 3 -#define EUR_CR_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_BREAKPOINT_TRAPPED_MASK 0x00000004U -#define EUR_CR_BREAKPOINT_TRAPPED_SHIFT 2 -#define EUR_CR_BREAKPOINT_TRAPPED_SIGNED 0 -/* Register EUR_CR_BREAKPOINT_TRAP_INFO0 */ -#define EUR_CR_BREAKPOINT_TRAP_INFO0 0x0F80 -#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT_TRAP_INFO1 */ -#define EUR_CR_BREAKPOINT_TRAP_INFO1 0x0F84 -#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U -#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 -#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 -#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U -#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 -#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 -#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U -#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 -#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 -#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U -#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 -#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 -#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U -#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 -#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_0 */ -#define EUR_CR_USE_CODE_BASE_0 0x0A0C -#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_1 */ -#define EUR_CR_USE_CODE_BASE_1 0x0A10 -#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_2 */ -#define EUR_CR_USE_CODE_BASE_2 0x0A14 -#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_3 */ -#define EUR_CR_USE_CODE_BASE_3 0x0A18 -#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_4 */ -#define EUR_CR_USE_CODE_BASE_4 0x0A1C -#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_5 */ -#define EUR_CR_USE_CODE_BASE_5 0x0A20 -#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_6 */ -#define EUR_CR_USE_CODE_BASE_6 0x0A24 -#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_7 */ -#define EUR_CR_USE_CODE_BASE_7 0x0A28 -#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_8 */ -#define EUR_CR_USE_CODE_BASE_8 0x0A2C -#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_9 */ -#define EUR_CR_USE_CODE_BASE_9 0x0A30 -#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_10 */ -#define EUR_CR_USE_CODE_BASE_10 0x0A34 -#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_11 */ -#define EUR_CR_USE_CODE_BASE_11 0x0A38 -#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_12 */ -#define EUR_CR_USE_CODE_BASE_12 0x0A3C -#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_13 */ -#define EUR_CR_USE_CODE_BASE_13 0x0A40 -#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_14 */ -#define EUR_CR_USE_CODE_BASE_14 0x0A44 -#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_15 */ -#define EUR_CR_USE_CODE_BASE_15 0x0A48 -#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0 -/* Table EUR_CR_USE_CODE_BASE */ -/* Register EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) -#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_SIGNED 0 -/* Number of entries in table EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 -#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 - -#endif /* _SGX543_V1_164DEFS_KM_H_ */ - diff --git a/pvr-source/services4/srvkm/hwdefs/sgx543defs.h b/pvr-source/services4/srvkm/hwdefs/sgx543defs.h deleted file mode 100755 index 0d3568d..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgx543defs.h +++ /dev/null @@ -1,1487 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for SGX543. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGX543DEFS_KM_H_ -#define _SGX543DEFS_KM_H_ - -/* Register EUR_CR_CLKGATECTL */ -#define EUR_CR_CLKGATECTL 0x0000 -#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL_ISP_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL_ISP2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL_TSP_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL_TE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL_MTE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL_DPM_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL_VDM_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL_PDS_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL_TA_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_MASK 0x00300000U -#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SHIFT 20 -#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0 -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28 -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SIGNED 0 -/* Register EUR_CR_CLKGATECTL2 */ -#define EUR_CR_CLKGATECTL2 0x0004 -#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL2_PBE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL2_USE0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL2_USE1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_MASK 0x00C00000U -#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SHIFT 22 -#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_MASK 0x03000000U -#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SHIFT 24 -#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_MASK 0x0C000000U -#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SHIFT 26 -#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SIGNED 0 -/* Register EUR_CR_CLKGATESTATUS */ -#define EUR_CR_CLKGATESTATUS 0x0008 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1 -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U -#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3 -#define EUR_CR_CLKGATESTATUS_TE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4 -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6 -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7 -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8 -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_MASK 0x00000200U -#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SHIFT 9 -#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10 -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11 -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12 -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13 -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15 -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16 -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17 -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19 -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_MASK 0x00200000U -#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SHIFT 21 -#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_MASK 0x00400000U -#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SHIFT 22 -#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_MASK 0x00800000U -#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SHIFT 23 -#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_MASK 0x01000000U -#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SHIFT 24 -#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SIGNED 0 -/* Register EUR_CR_CLKGATECTLOVR */ -#define EUR_CR_CLKGATECTLOVR 0x000C -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2 -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6 -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8 -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12 -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14 -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16 -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_MASK 0x00300000U -#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SHIFT 20 -#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SIGNED 0 -/* Register EUR_CR_POWER */ -#define EUR_CR_POWER 0x001C -#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U -#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0 -#define EUR_CR_POWER_PIPE_DISABLE_SIGNED 0 -/* Register EUR_CR_CORE_ID */ -#define EUR_CR_CORE_ID 0x0020 -#define EUR_CR_CORE_ID_CONFIG_MULTI_MASK 0x00000001U -#define EUR_CR_CORE_ID_CONFIG_MULTI_SHIFT 0 -#define EUR_CR_CORE_ID_CONFIG_MULTI_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_BASE_MASK 0x00000002U -#define EUR_CR_CORE_ID_CONFIG_BASE_SHIFT 1 -#define EUR_CR_CORE_ID_CONFIG_BASE_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_MASK 0x000000FCU -#define EUR_CR_CORE_ID_CONFIG_SHIFT 2 -#define EUR_CR_CORE_ID_CONFIG_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_CORES_MASK 0x00000F00U -#define EUR_CR_CORE_ID_CONFIG_CORES_SHIFT 8 -#define EUR_CR_CORE_ID_CONFIG_CORES_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_SLC_MASK 0x0000F000U -#define EUR_CR_CORE_ID_CONFIG_SLC_SHIFT 12 -#define EUR_CR_CORE_ID_CONFIG_SLC_SIGNED 0 -#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U -#define EUR_CR_CORE_ID_ID_SHIFT 16 -#define EUR_CR_CORE_ID_ID_SIGNED 0 -/* Register EUR_CR_CORE_REVISION */ -#define EUR_CR_CORE_REVISION 0x0024 -#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU -#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 -#define EUR_CR_CORE_REVISION_MAINTENANCE_SIGNED 0 -#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U -#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8 -#define EUR_CR_CORE_REVISION_MINOR_SIGNED 0 -#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U -#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 -#define EUR_CR_CORE_REVISION_MAJOR_SIGNED 0 -#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U -#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 -#define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0 -/* Register EUR_CR_DESIGNER_REV_FIELD1 */ -#define EUR_CR_DESIGNER_REV_FIELD1 0x0028 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0 -/* Register EUR_CR_DESIGNER_REV_FIELD2 */ -#define EUR_CR_DESIGNER_REV_FIELD2 0x002C -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0 -/* Register EUR_CR_SOFT_RESET */ -#define EUR_CR_SOFT_RESET 0x0080 -#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U -#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 -#define EUR_CR_SOFT_RESET_BIF_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U -#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1 -#define EUR_CR_SOFT_RESET_VDM_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U -#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 -#define EUR_CR_SOFT_RESET_DPM_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U -#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3 -#define EUR_CR_SOFT_RESET_TE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U -#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4 -#define EUR_CR_SOFT_RESET_MTE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U -#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5 -#define EUR_CR_SOFT_RESET_ISP_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U -#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6 -#define EUR_CR_SOFT_RESET_ISP2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U -#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7 -#define EUR_CR_SOFT_RESET_TSP_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U -#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8 -#define EUR_CR_SOFT_RESET_PDS_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U -#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9 -#define EUR_CR_SOFT_RESET_PBE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK 0x00000400U -#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SHIFT 10 -#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11 -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U -#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13 -#define EUR_CR_SOFT_RESET_ITR_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U -#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14 -#define EUR_CR_SOFT_RESET_TEX_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U -#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15 -#define EUR_CR_SOFT_RESET_USE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16 -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U -#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17 -#define EUR_CR_SOFT_RESET_TA_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK 0x00040000U -#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SHIFT 18 -#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK 0x00080000U -#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SHIFT 19 -#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_ENABLE2 */ -#define EUR_CR_EVENT_HOST_ENABLE2 0x0110 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_CLEAR2 */ -#define EUR_CR_EVENT_HOST_CLEAR2 0x0114 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_STATUS2 */ -#define EUR_CR_EVENT_STATUS2 0x0118 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SHIFT 9 -#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 -#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SHIFT 7 -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SHIFT 6 -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 -#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_STATUS */ -#define EUR_CR_EVENT_STATUS 0x012C -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 -#define EUR_CR_EVENT_STATUS_TIMER_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_STATUS_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_STATUS_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_ENABLE */ -#define EUR_CR_EVENT_HOST_ENABLE 0x0130 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_CLEAR */ -#define EUR_CR_EVENT_HOST_CLEAR 0x0134 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_TIMER */ -#define EUR_CR_TIMER 0x0144 -#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU -#define EUR_CR_TIMER_VALUE_SHIFT 0 -#define EUR_CR_TIMER_VALUE_SIGNED 0 -/* Register EUR_CR_EVENT_KICK1 */ -#define EUR_CR_EVENT_KICK1 0x0AB0 -#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU -#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK1_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_KICK2 */ -#define EUR_CR_EVENT_KICK2 0x0AC0 -#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK2_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_KICKER */ -#define EUR_CR_EVENT_KICKER 0x0AC4 -#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 -#define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0 -/* Register EUR_CR_EVENT_KICK */ -#define EUR_CR_EVENT_KICK 0x0AC8 -#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_TIMER */ -#define EUR_CR_EVENT_TIMER 0x0ACC -#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U -#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 -#define EUR_CR_EVENT_TIMER_ENABLE_SIGNED 0 -#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU -#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 -#define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0 -/* Register EUR_CR_PDS_INV0 */ -#define EUR_CR_PDS_INV0 0x0AD0 -#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV0_DSC_SHIFT 0 -#define EUR_CR_PDS_INV0_DSC_SIGNED 0 -/* Register EUR_CR_PDS_INV1 */ -#define EUR_CR_PDS_INV1 0x0AD4 -#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV1_DSC_SHIFT 0 -#define EUR_CR_PDS_INV1_DSC_SIGNED 0 -/* Register EUR_CR_EVENT_KICK3 */ -#define EUR_CR_EVENT_KICK3 0x0AD8 -#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK3_NOW_SIGNED 0 -/* Register EUR_CR_PDS_INV3 */ -#define EUR_CR_PDS_INV3 0x0ADC -#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV3_DSC_SHIFT 0 -#define EUR_CR_PDS_INV3_DSC_SIGNED 0 -/* Register EUR_CR_PDS_INV_CSC */ -#define EUR_CR_PDS_INV_CSC 0x0AE0 -#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U -#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 -#define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0 -/* Register EUR_CR_BIF_CTRL */ -#define EUR_CR_BIF_CTRL 0x0C00 -#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U -#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 -#define EUR_CR_BIF_CTRL_NOREORDER_SIGNED 0 -#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U -#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1 -#define EUR_CR_BIF_CTRL_PAUSE_SIGNED 0 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_MASK 0x00000400U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SHIFT 10 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_MASK 0x00010000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SHIFT 16 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_MASK 0x00020000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SHIFT 17 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_MASK 0x00040000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SHIFT 18 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0 -/* Register EUR_CR_BIF_INT_STAT */ -#define EUR_CR_BIF_INT_STAT 0x0C04 -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x00003FFFU -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0 -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SIGNED 0 -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK 0x00070000U -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SHIFT 16 -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SIGNED 0 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0 -/* Register EUR_CR_BIF_FAULT */ -#define EUR_CR_BIF_FAULT 0x0C08 -#define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU -#define EUR_CR_BIF_FAULT_CID_SHIFT 0 -#define EUR_CR_BIF_FAULT_CID_SIGNED 0 -#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U -#define EUR_CR_BIF_FAULT_SB_SHIFT 4 -#define EUR_CR_BIF_FAULT_SB_SIGNED 0 -#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 -#define EUR_CR_BIF_FAULT_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_TILE0 */ -#define EUR_CR_BIF_TILE0 0x0C0C -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE0_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE0_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE1 */ -#define EUR_CR_BIF_TILE1 0x0C10 -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE1_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE1_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE2 */ -#define EUR_CR_BIF_TILE2 0x0C14 -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE2_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE2_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE3 */ -#define EUR_CR_BIF_TILE3 0x0C18 -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE3_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE3_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE4 */ -#define EUR_CR_BIF_TILE4 0x0C1C -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE4_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE4_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE5 */ -#define EUR_CR_BIF_TILE5 0x0C20 -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE5_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE5_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE6 */ -#define EUR_CR_BIF_TILE6 0x0C24 -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE6_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE6_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE7 */ -#define EUR_CR_BIF_TILE7 0x0C28 -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE7_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE7_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE8 */ -#define EUR_CR_BIF_TILE8 0x0C2C -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE8_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE8_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE9 */ -#define EUR_CR_BIF_TILE9 0x0C30 -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE9_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE9_CFG_SIGNED 0 -/* Register EUR_CR_BIF_CTRL_INVAL */ -#define EUR_CR_BIF_CTRL_INVAL 0x0C34 -#define EUR_CR_BIF_CTRL_INVAL_PTE_MASK 0x00000004U -#define EUR_CR_BIF_CTRL_INVAL_PTE_SHIFT 2 -#define EUR_CR_BIF_CTRL_INVAL_PTE_SIGNED 0 -#define EUR_CR_BIF_CTRL_INVAL_ALL_MASK 0x00000008U -#define EUR_CR_BIF_CTRL_INVAL_ALL_SHIFT 3 -#define EUR_CR_BIF_CTRL_INVAL_ALL_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE1 */ -#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38 -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE2 */ -#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE3 */ -#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40 -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE4 */ -#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44 -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE5 */ -#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48 -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE6 */ -#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE7 */ -#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50 -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_BANK_SET */ -#define EUR_CR_BIF_BANK_SET 0x0C74 -#define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U -#define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0 -#define EUR_CR_BIF_BANK_SET_SELECT_2D_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_3D_MASK 0x0000000CU -#define EUR_CR_BIF_BANK_SET_SELECT_3D_SHIFT 2 -#define EUR_CR_BIF_BANK_SET_SELECT_3D_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_MASK 0x00000010U -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SHIFT 4 -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_TA_MASK 0x000000C0U -#define EUR_CR_BIF_BANK_SET_SELECT_TA_SHIFT 6 -#define EUR_CR_BIF_BANK_SET_SELECT_TA_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_MASK 0x00000100U -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SHIFT 8 -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9 -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0 -/* Register EUR_CR_BIF_BANK0 */ -#define EUR_CR_BIF_BANK0 0x0C78 -#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK0_INDEX_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK0_INDEX_TA_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK0_INDEX_3D_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_PTLA_MASK 0x000F0000U -#define EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT 16 -#define EUR_CR_BIF_BANK0_INDEX_PTLA_SIGNED 0 -/* Register EUR_CR_BIF_BANK1 */ -#define EUR_CR_BIF_BANK1 0x0C7C -#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK1_INDEX_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK1_INDEX_TA_SIGNED 0 -#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ -#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_TA_REQ_BASE */ -#define EUR_CR_BIF_TA_REQ_BASE 0x0C90 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_MEM_REQ_STAT */ -#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0 -/* Register EUR_CR_BIF_3D_REQ_BASE */ -#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_ZLS_REQ_BASE */ -#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_BANK_STATUS */ -#define EUR_CR_BIF_BANK_STATUS 0x0CB4 -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0 -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SIGNED 0 -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0 -/* Register EUR_CR_BIF_MMU_CTRL */ -#define EUR_CR_BIF_MMU_CTRL 0x0CD0 -#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U -#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0 -#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U -#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1 -#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_MASK 0x00000008U -#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SHIFT 3 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U -#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_MASK 0x00000020U -#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SHIFT 5 -#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SIGNED 0 -/* Register EUR_CR_2D_BLIT_STATUS */ -#define EUR_CR_2D_BLIT_STATUS 0x0E04 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SIGNED 0 -#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U -#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 -#define EUR_CR_2D_BLIT_STATUS_BUSY_SIGNED 0 -/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ -#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SIGNED 0 -/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ -#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SIGNED 0 -/* Register EUR_CR_BREAKPOINT0_START */ -#define EUR_CR_BREAKPOINT0_START 0x0F44 -#define EUR_CR_BREAKPOINT0_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT0_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT0_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT0_END */ -#define EUR_CR_BREAKPOINT0_END 0x0F48 -#define EUR_CR_BREAKPOINT0_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT0_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT0_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT0 */ -#define EUR_CR_BREAKPOINT0 0x0F4C -#define EUR_CR_BREAKPOINT0_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT0_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT0_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT1_START */ -#define EUR_CR_BREAKPOINT1_START 0x0F50 -#define EUR_CR_BREAKPOINT1_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT1_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT1_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT1_END */ -#define EUR_CR_BREAKPOINT1_END 0x0F54 -#define EUR_CR_BREAKPOINT1_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT1_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT1_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT1 */ -#define EUR_CR_BREAKPOINT1 0x0F58 -#define EUR_CR_BREAKPOINT1_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT1_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT1_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT2_START */ -#define EUR_CR_BREAKPOINT2_START 0x0F5C -#define EUR_CR_BREAKPOINT2_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT2_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT2_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT2_END */ -#define EUR_CR_BREAKPOINT2_END 0x0F60 -#define EUR_CR_BREAKPOINT2_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT2_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT2_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT2 */ -#define EUR_CR_BREAKPOINT2 0x0F64 -#define EUR_CR_BREAKPOINT2_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT2_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT2_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT3_START */ -#define EUR_CR_BREAKPOINT3_START 0x0F68 -#define EUR_CR_BREAKPOINT3_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT3_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT3_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT3_END */ -#define EUR_CR_BREAKPOINT3_END 0x0F6C -#define EUR_CR_BREAKPOINT3_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT3_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT3_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT3 */ -#define EUR_CR_BREAKPOINT3 0x0F70 -#define EUR_CR_BREAKPOINT3_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT3_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT3_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT_READ */ -#define EUR_CR_BREAKPOINT_READ 0x0F74 -#define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0 -/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP */ -#define EUR_CR_PARTITION_BREAKPOINT_TRAP 0x0F78 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 -/* Register EUR_CR_PARTITION_BREAKPOINT */ -#define EUR_CR_PARTITION_BREAKPOINT 0x0F7C -#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_MASK 0x000003C0U -#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SHIFT 6 -#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_ID_MASK 0x00000030U -#define EUR_CR_PARTITION_BREAKPOINT_ID_SHIFT 4 -#define EUR_CR_PARTITION_BREAKPOINT_ID_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_MASK 0x00000008U -#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_SHIFT 3 -#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_MASK 0x00000004U -#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SHIFT 2 -#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SIGNED 0 -/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 */ -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 0x0F80 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 -/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 */ -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 0x0F84 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_0 */ -#define EUR_CR_USE_CODE_BASE_0 0x0A0C -#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_1 */ -#define EUR_CR_USE_CODE_BASE_1 0x0A10 -#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_2 */ -#define EUR_CR_USE_CODE_BASE_2 0x0A14 -#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_3 */ -#define EUR_CR_USE_CODE_BASE_3 0x0A18 -#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_4 */ -#define EUR_CR_USE_CODE_BASE_4 0x0A1C -#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_5 */ -#define EUR_CR_USE_CODE_BASE_5 0x0A20 -#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_6 */ -#define EUR_CR_USE_CODE_BASE_6 0x0A24 -#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_7 */ -#define EUR_CR_USE_CODE_BASE_7 0x0A28 -#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_8 */ -#define EUR_CR_USE_CODE_BASE_8 0x0A2C -#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_9 */ -#define EUR_CR_USE_CODE_BASE_9 0x0A30 -#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_10 */ -#define EUR_CR_USE_CODE_BASE_10 0x0A34 -#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_11 */ -#define EUR_CR_USE_CODE_BASE_11 0x0A38 -#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_12 */ -#define EUR_CR_USE_CODE_BASE_12 0x0A3C -#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_13 */ -#define EUR_CR_USE_CODE_BASE_13 0x0A40 -#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_14 */ -#define EUR_CR_USE_CODE_BASE_14 0x0A44 -#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_15 */ -#define EUR_CR_USE_CODE_BASE_15 0x0A48 -#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0 -/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP */ -#define EUR_CR_PIPE0_BREAKPOINT_TRAP 0x0F88 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 -/* Register EUR_CR_PIPE0_BREAKPOINT */ -#define EUR_CR_PIPE0_BREAKPOINT 0x0F8C -#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_MASK 0x000003C0U -#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SHIFT 6 -#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_ID_MASK 0x00000030U -#define EUR_CR_PIPE0_BREAKPOINT_ID_SHIFT 4 -#define EUR_CR_PIPE0_BREAKPOINT_ID_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_MASK 0x00000008U -#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_SHIFT 3 -#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_MASK 0x00000004U -#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SHIFT 2 -#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SIGNED 0 -/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 */ -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 0x0F90 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 -/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 */ -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 0x0F94 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 -/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP */ -#define EUR_CR_PIPE1_BREAKPOINT_TRAP 0x0F98 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 -/* Register EUR_CR_PIPE1_BREAKPOINT */ -#define EUR_CR_PIPE1_BREAKPOINT 0x0F9C -#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_MASK 0x000003C0U -#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SHIFT 6 -#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_ID_MASK 0x00000030U -#define EUR_CR_PIPE1_BREAKPOINT_ID_SHIFT 4 -#define EUR_CR_PIPE1_BREAKPOINT_ID_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_MASK 0x00000008U -#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_SHIFT 3 -#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_MASK 0x00000004U -#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SHIFT 2 -#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SIGNED 0 -/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 */ -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 0x0FA0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 -/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 */ -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 0x0FA4 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 -/* Table EUR_CR_USE_CODE_BASE */ -/* Register EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) -#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_SIGNED 0 -/* Number of entries in table EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 -#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 - -#endif /* _SGX543DEFS_KM_H_ */ - diff --git a/pvr-source/services4/srvkm/hwdefs/sgx544defs.h b/pvr-source/services4/srvkm/hwdefs/sgx544defs.h deleted file mode 100755 index 79efcbc..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgx544defs.h +++ /dev/null @@ -1,1487 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for SGX544. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGX544DEFS_KM_H_ -#define _SGX544DEFS_KM_H_ - -/* Register EUR_CR_CLKGATECTL */ -#define EUR_CR_CLKGATECTL 0x0000 -#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL_ISP_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL_ISP2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL_TSP_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL_TE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL_MTE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL_DPM_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL_VDM_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL_PDS_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL_TA_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_MASK 0x00300000U -#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SHIFT 20 -#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0 -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28 -#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SIGNED 0 -/* Register EUR_CR_CLKGATECTL2 */ -#define EUR_CR_CLKGATECTL2 0x0004 -#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL2_PBE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL2_USE0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL2_USE1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_MASK 0x00C00000U -#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SHIFT 22 -#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_MASK 0x03000000U -#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SHIFT 24 -#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_MASK 0x0C000000U -#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SHIFT 26 -#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SIGNED 0 -/* Register EUR_CR_CLKGATESTATUS */ -#define EUR_CR_CLKGATESTATUS 0x0008 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1 -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U -#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3 -#define EUR_CR_CLKGATESTATUS_TE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4 -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6 -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7 -#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8 -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_MASK 0x00000200U -#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SHIFT 9 -#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10 -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11 -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12 -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13 -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15 -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16 -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17 -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19 -#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20 -#define EUR_CR_CLKGATESTATUS_TA_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_MASK 0x00200000U -#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SHIFT 21 -#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_MASK 0x00400000U -#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SHIFT 22 -#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_MASK 0x00800000U -#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SHIFT 23 -#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_MASK 0x01000000U -#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SHIFT 24 -#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SIGNED 0 -/* Register EUR_CR_CLKGATECTLOVR */ -#define EUR_CR_CLKGATECTLOVR 0x000C -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2 -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6 -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8 -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12 -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14 -#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16 -#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18 -#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_MASK 0x00300000U -#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SHIFT 20 -#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SIGNED 0 -/* Register EUR_CR_POWER */ -#define EUR_CR_POWER 0x001C -#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U -#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0 -#define EUR_CR_POWER_PIPE_DISABLE_SIGNED 0 -/* Register EUR_CR_CORE_ID */ -#define EUR_CR_CORE_ID 0x0020 -#define EUR_CR_CORE_ID_CONFIG_MULTI_MASK 0x00000001U -#define EUR_CR_CORE_ID_CONFIG_MULTI_SHIFT 0 -#define EUR_CR_CORE_ID_CONFIG_MULTI_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_BASE_MASK 0x00000002U -#define EUR_CR_CORE_ID_CONFIG_BASE_SHIFT 1 -#define EUR_CR_CORE_ID_CONFIG_BASE_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_MASK 0x000000FCU -#define EUR_CR_CORE_ID_CONFIG_SHIFT 2 -#define EUR_CR_CORE_ID_CONFIG_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_CORES_MASK 0x00000F00U -#define EUR_CR_CORE_ID_CONFIG_CORES_SHIFT 8 -#define EUR_CR_CORE_ID_CONFIG_CORES_SIGNED 0 -#define EUR_CR_CORE_ID_CONFIG_SLC_MASK 0x0000F000U -#define EUR_CR_CORE_ID_CONFIG_SLC_SHIFT 12 -#define EUR_CR_CORE_ID_CONFIG_SLC_SIGNED 0 -#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U -#define EUR_CR_CORE_ID_ID_SHIFT 16 -#define EUR_CR_CORE_ID_ID_SIGNED 0 -/* Register EUR_CR_CORE_REVISION */ -#define EUR_CR_CORE_REVISION 0x0024 -#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU -#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 -#define EUR_CR_CORE_REVISION_MAINTENANCE_SIGNED 0 -#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U -#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8 -#define EUR_CR_CORE_REVISION_MINOR_SIGNED 0 -#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U -#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 -#define EUR_CR_CORE_REVISION_MAJOR_SIGNED 0 -#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U -#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 -#define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0 -/* Register EUR_CR_DESIGNER_REV_FIELD1 */ -#define EUR_CR_DESIGNER_REV_FIELD1 0x0028 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0 -/* Register EUR_CR_DESIGNER_REV_FIELD2 */ -#define EUR_CR_DESIGNER_REV_FIELD2 0x002C -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0 -/* Register EUR_CR_SOFT_RESET */ -#define EUR_CR_SOFT_RESET 0x0080 -#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U -#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 -#define EUR_CR_SOFT_RESET_BIF_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U -#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1 -#define EUR_CR_SOFT_RESET_VDM_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U -#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 -#define EUR_CR_SOFT_RESET_DPM_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U -#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3 -#define EUR_CR_SOFT_RESET_TE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U -#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4 -#define EUR_CR_SOFT_RESET_MTE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U -#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5 -#define EUR_CR_SOFT_RESET_ISP_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U -#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6 -#define EUR_CR_SOFT_RESET_ISP2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U -#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7 -#define EUR_CR_SOFT_RESET_TSP_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U -#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8 -#define EUR_CR_SOFT_RESET_PDS_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U -#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9 -#define EUR_CR_SOFT_RESET_PBE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK 0x00000400U -#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SHIFT 10 -#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11 -#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U -#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13 -#define EUR_CR_SOFT_RESET_ITR_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U -#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14 -#define EUR_CR_SOFT_RESET_TEX_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U -#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15 -#define EUR_CR_SOFT_RESET_USE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16 -#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U -#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17 -#define EUR_CR_SOFT_RESET_TA_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK 0x00040000U -#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SHIFT 18 -#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK 0x00080000U -#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SHIFT 19 -#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_ENABLE2 */ -#define EUR_CR_EVENT_HOST_ENABLE2 0x0110 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_CLEAR2 */ -#define EUR_CR_EVENT_HOST_CLEAR2 0x0114 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_STATUS2 */ -#define EUR_CR_EVENT_STATUS2 0x0118 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 -#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SHIFT 9 -#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 -#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SHIFT 7 -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SHIFT 6 -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 -#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_STATUS */ -#define EUR_CR_EVENT_STATUS 0x012C -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 -#define EUR_CR_EVENT_STATUS_TIMER_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_STATUS_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_STATUS_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_ENABLE */ -#define EUR_CR_EVENT_HOST_ENABLE 0x0130 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_CLEAR */ -#define EUR_CR_EVENT_HOST_CLEAR 0x0134 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_TIMER */ -#define EUR_CR_TIMER 0x0144 -#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU -#define EUR_CR_TIMER_VALUE_SHIFT 0 -#define EUR_CR_TIMER_VALUE_SIGNED 0 -/* Register EUR_CR_EVENT_KICK1 */ -#define EUR_CR_EVENT_KICK1 0x0AB0 -#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU -#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK1_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_KICK2 */ -#define EUR_CR_EVENT_KICK2 0x0AC0 -#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK2_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_KICKER */ -#define EUR_CR_EVENT_KICKER 0x0AC4 -#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 -#define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0 -/* Register EUR_CR_EVENT_KICK */ -#define EUR_CR_EVENT_KICK 0x0AC8 -#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_TIMER */ -#define EUR_CR_EVENT_TIMER 0x0ACC -#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U -#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 -#define EUR_CR_EVENT_TIMER_ENABLE_SIGNED 0 -#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU -#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 -#define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0 -/* Register EUR_CR_PDS_INV0 */ -#define EUR_CR_PDS_INV0 0x0AD0 -#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV0_DSC_SHIFT 0 -#define EUR_CR_PDS_INV0_DSC_SIGNED 0 -/* Register EUR_CR_PDS_INV1 */ -#define EUR_CR_PDS_INV1 0x0AD4 -#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV1_DSC_SHIFT 0 -#define EUR_CR_PDS_INV1_DSC_SIGNED 0 -/* Register EUR_CR_EVENT_KICK3 */ -#define EUR_CR_EVENT_KICK3 0x0AD8 -#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK3_NOW_SIGNED 0 -/* Register EUR_CR_PDS_INV3 */ -#define EUR_CR_PDS_INV3 0x0ADC -#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV3_DSC_SHIFT 0 -#define EUR_CR_PDS_INV3_DSC_SIGNED 0 -/* Register EUR_CR_PDS_INV_CSC */ -#define EUR_CR_PDS_INV_CSC 0x0AE0 -#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U -#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 -#define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0 -/* Register EUR_CR_BIF_CTRL */ -#define EUR_CR_BIF_CTRL 0x0C00 -#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U -#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 -#define EUR_CR_BIF_CTRL_NOREORDER_SIGNED 0 -#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U -#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1 -#define EUR_CR_BIF_CTRL_PAUSE_SIGNED 0 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_MASK 0x00000400U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SHIFT 10 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_MASK 0x00010000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SHIFT 16 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_MASK 0x00020000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SHIFT 17 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_MASK 0x00040000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SHIFT 18 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0 -/* Register EUR_CR_BIF_INT_STAT */ -#define EUR_CR_BIF_INT_STAT 0x0C04 -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x00003FFFU -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0 -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SIGNED 0 -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK 0x00070000U -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SHIFT 16 -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SIGNED 0 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0 -/* Register EUR_CR_BIF_FAULT */ -#define EUR_CR_BIF_FAULT 0x0C08 -#define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU -#define EUR_CR_BIF_FAULT_CID_SHIFT 0 -#define EUR_CR_BIF_FAULT_CID_SIGNED 0 -#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U -#define EUR_CR_BIF_FAULT_SB_SHIFT 4 -#define EUR_CR_BIF_FAULT_SB_SIGNED 0 -#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 -#define EUR_CR_BIF_FAULT_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_TILE0 */ -#define EUR_CR_BIF_TILE0 0x0C0C -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE0_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE0_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE1 */ -#define EUR_CR_BIF_TILE1 0x0C10 -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE1_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE1_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE2 */ -#define EUR_CR_BIF_TILE2 0x0C14 -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE2_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE2_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE3 */ -#define EUR_CR_BIF_TILE3 0x0C18 -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE3_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE3_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE4 */ -#define EUR_CR_BIF_TILE4 0x0C1C -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE4_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE4_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE5 */ -#define EUR_CR_BIF_TILE5 0x0C20 -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE5_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE5_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE6 */ -#define EUR_CR_BIF_TILE6 0x0C24 -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE6_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE6_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE7 */ -#define EUR_CR_BIF_TILE7 0x0C28 -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE7_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE7_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE8 */ -#define EUR_CR_BIF_TILE8 0x0C2C -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE8_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE8_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE9 */ -#define EUR_CR_BIF_TILE9 0x0C30 -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE9_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE9_CFG_SIGNED 0 -/* Register EUR_CR_BIF_CTRL_INVAL */ -#define EUR_CR_BIF_CTRL_INVAL 0x0C34 -#define EUR_CR_BIF_CTRL_INVAL_PTE_MASK 0x00000004U -#define EUR_CR_BIF_CTRL_INVAL_PTE_SHIFT 2 -#define EUR_CR_BIF_CTRL_INVAL_PTE_SIGNED 0 -#define EUR_CR_BIF_CTRL_INVAL_ALL_MASK 0x00000008U -#define EUR_CR_BIF_CTRL_INVAL_ALL_SHIFT 3 -#define EUR_CR_BIF_CTRL_INVAL_ALL_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE1 */ -#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38 -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE2 */ -#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE3 */ -#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40 -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE4 */ -#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44 -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE5 */ -#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48 -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE6 */ -#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE7 */ -#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50 -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_BANK_SET */ -#define EUR_CR_BIF_BANK_SET 0x0C74 -#define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U -#define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0 -#define EUR_CR_BIF_BANK_SET_SELECT_2D_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_3D_MASK 0x0000000CU -#define EUR_CR_BIF_BANK_SET_SELECT_3D_SHIFT 2 -#define EUR_CR_BIF_BANK_SET_SELECT_3D_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_MASK 0x00000010U -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SHIFT 4 -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_TA_MASK 0x000000C0U -#define EUR_CR_BIF_BANK_SET_SELECT_TA_SHIFT 6 -#define EUR_CR_BIF_BANK_SET_SELECT_TA_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_MASK 0x00000100U -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SHIFT 8 -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9 -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0 -/* Register EUR_CR_BIF_BANK0 */ -#define EUR_CR_BIF_BANK0 0x0C78 -#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK0_INDEX_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK0_INDEX_TA_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK0_INDEX_3D_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_PTLA_MASK 0x000F0000U -#define EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT 16 -#define EUR_CR_BIF_BANK0_INDEX_PTLA_SIGNED 0 -/* Register EUR_CR_BIF_BANK1 */ -#define EUR_CR_BIF_BANK1 0x0C7C -#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK1_INDEX_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK1_INDEX_TA_SIGNED 0 -#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ -#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_TA_REQ_BASE */ -#define EUR_CR_BIF_TA_REQ_BASE 0x0C90 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_MEM_REQ_STAT */ -#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0 -/* Register EUR_CR_BIF_3D_REQ_BASE */ -#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_ZLS_REQ_BASE */ -#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_BANK_STATUS */ -#define EUR_CR_BIF_BANK_STATUS 0x0CB4 -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0 -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SIGNED 0 -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0 -/* Register EUR_CR_BIF_MMU_CTRL */ -#define EUR_CR_BIF_MMU_CTRL 0x0CD0 -#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U -#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0 -#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U -#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1 -#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_MASK 0x00000008U -#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SHIFT 3 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U -#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4 -#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0 -#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_MASK 0x00000020U -#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SHIFT 5 -#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SIGNED 0 -/* Register EUR_CR_2D_BLIT_STATUS */ -#define EUR_CR_2D_BLIT_STATUS 0x0E04 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SIGNED 0 -#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U -#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 -#define EUR_CR_2D_BLIT_STATUS_BUSY_SIGNED 0 -/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ -#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SIGNED 0 -/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ -#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SIGNED 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SIGNED 0 -/* Register EUR_CR_BREAKPOINT0_START */ -#define EUR_CR_BREAKPOINT0_START 0x0F44 -#define EUR_CR_BREAKPOINT0_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT0_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT0_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT0_END */ -#define EUR_CR_BREAKPOINT0_END 0x0F48 -#define EUR_CR_BREAKPOINT0_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT0_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT0_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT0 */ -#define EUR_CR_BREAKPOINT0 0x0F4C -#define EUR_CR_BREAKPOINT0_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT0_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT0_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT1_START */ -#define EUR_CR_BREAKPOINT1_START 0x0F50 -#define EUR_CR_BREAKPOINT1_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT1_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT1_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT1_END */ -#define EUR_CR_BREAKPOINT1_END 0x0F54 -#define EUR_CR_BREAKPOINT1_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT1_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT1_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT1 */ -#define EUR_CR_BREAKPOINT1 0x0F58 -#define EUR_CR_BREAKPOINT1_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT1_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT1_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT2_START */ -#define EUR_CR_BREAKPOINT2_START 0x0F5C -#define EUR_CR_BREAKPOINT2_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT2_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT2_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT2_END */ -#define EUR_CR_BREAKPOINT2_END 0x0F60 -#define EUR_CR_BREAKPOINT2_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT2_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT2_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT2 */ -#define EUR_CR_BREAKPOINT2 0x0F64 -#define EUR_CR_BREAKPOINT2_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT2_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT2_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT3_START */ -#define EUR_CR_BREAKPOINT3_START 0x0F68 -#define EUR_CR_BREAKPOINT3_START_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT3_START_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT3_START_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT3_END */ -#define EUR_CR_BREAKPOINT3_END 0x0F6C -#define EUR_CR_BREAKPOINT3_END_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT3_END_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT3_END_ADDRESS_SIGNED 0 -/* Register EUR_CR_BREAKPOINT3 */ -#define EUR_CR_BREAKPOINT3 0x0F70 -#define EUR_CR_BREAKPOINT3_MASK_DM_MASK 0x00000038U -#define EUR_CR_BREAKPOINT3_MASK_DM_SHIFT 3 -#define EUR_CR_BREAKPOINT3_MASK_DM_SIGNED 0 -#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_MASK 0x00000004U -#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SHIFT 2 -#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_MASK 0x00000002U -#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SHIFT 1 -#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SIGNED 0 -#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_MASK 0x00000001U -#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SHIFT 0 -#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SIGNED 0 -/* Register EUR_CR_BREAKPOINT_READ */ -#define EUR_CR_BREAKPOINT_READ 0x0F74 -#define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4 -#define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0 -/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP */ -#define EUR_CR_PARTITION_BREAKPOINT_TRAP 0x0F78 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 -/* Register EUR_CR_PARTITION_BREAKPOINT */ -#define EUR_CR_PARTITION_BREAKPOINT 0x0F7C -#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_MASK 0x000003C0U -#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SHIFT 6 -#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_ID_MASK 0x00000030U -#define EUR_CR_PARTITION_BREAKPOINT_ID_SHIFT 4 -#define EUR_CR_PARTITION_BREAKPOINT_ID_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_MASK 0x00000008U -#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_SHIFT 3 -#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_MASK 0x00000004U -#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SHIFT 2 -#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SIGNED 0 -/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 */ -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 0x0F80 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 -/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 */ -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 0x0F84 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 -#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_0 */ -#define EUR_CR_USE_CODE_BASE_0 0x0A0C -#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_1 */ -#define EUR_CR_USE_CODE_BASE_1 0x0A10 -#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_2 */ -#define EUR_CR_USE_CODE_BASE_2 0x0A14 -#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_3 */ -#define EUR_CR_USE_CODE_BASE_3 0x0A18 -#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_4 */ -#define EUR_CR_USE_CODE_BASE_4 0x0A1C -#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_5 */ -#define EUR_CR_USE_CODE_BASE_5 0x0A20 -#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_6 */ -#define EUR_CR_USE_CODE_BASE_6 0x0A24 -#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_7 */ -#define EUR_CR_USE_CODE_BASE_7 0x0A28 -#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_8 */ -#define EUR_CR_USE_CODE_BASE_8 0x0A2C -#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_9 */ -#define EUR_CR_USE_CODE_BASE_9 0x0A30 -#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_10 */ -#define EUR_CR_USE_CODE_BASE_10 0x0A34 -#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_11 */ -#define EUR_CR_USE_CODE_BASE_11 0x0A38 -#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_12 */ -#define EUR_CR_USE_CODE_BASE_12 0x0A3C -#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_13 */ -#define EUR_CR_USE_CODE_BASE_13 0x0A40 -#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_14 */ -#define EUR_CR_USE_CODE_BASE_14 0x0A44 -#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_15 */ -#define EUR_CR_USE_CODE_BASE_15 0x0A48 -#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0 -/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP */ -#define EUR_CR_PIPE0_BREAKPOINT_TRAP 0x0F88 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 -/* Register EUR_CR_PIPE0_BREAKPOINT */ -#define EUR_CR_PIPE0_BREAKPOINT 0x0F8C -#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_MASK 0x000003C0U -#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SHIFT 6 -#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_ID_MASK 0x00000030U -#define EUR_CR_PIPE0_BREAKPOINT_ID_SHIFT 4 -#define EUR_CR_PIPE0_BREAKPOINT_ID_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_MASK 0x00000008U -#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_SHIFT 3 -#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_MASK 0x00000004U -#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SHIFT 2 -#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SIGNED 0 -/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 */ -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 0x0F90 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 -/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 */ -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 0x0F94 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 -#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 -/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP */ -#define EUR_CR_PIPE1_BREAKPOINT_TRAP 0x0F98 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 -/* Register EUR_CR_PIPE1_BREAKPOINT */ -#define EUR_CR_PIPE1_BREAKPOINT 0x0F9C -#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_MASK 0x000003C0U -#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SHIFT 6 -#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_ID_MASK 0x00000030U -#define EUR_CR_PIPE1_BREAKPOINT_ID_SHIFT 4 -#define EUR_CR_PIPE1_BREAKPOINT_ID_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_MASK 0x00000008U -#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_SHIFT 3 -#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_MASK 0x00000004U -#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SHIFT 2 -#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SIGNED 0 -/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 */ -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 0x0FA0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 -/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 */ -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 0x0FA4 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 -#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 -/* Table EUR_CR_USE_CODE_BASE */ -/* Register EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) -#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_MASK 0x0C000000U -#define EUR_CR_USE_CODE_BASE_DM_SHIFT 26 -#define EUR_CR_USE_CODE_BASE_DM_SIGNED 0 -/* Number of entries in table EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 -#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 - -#endif /* _SGX544DEFS_KM_H_ */ - diff --git a/pvr-source/services4/srvkm/hwdefs/sgx545defs.h b/pvr-source/services4/srvkm/hwdefs/sgx545defs.h deleted file mode 100755 index c5adee2..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgx545defs.h +++ /dev/null @@ -1,1290 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for SGX545. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGX545DEFS_KM_H_ -#define _SGX545DEFS_KM_H_ - -/* Register EUR_CR_CLKGATECTL */ -#define EUR_CR_CLKGATECTL 0x0000 -#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL_ISP_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL_ISP2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL_TSP_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL_TE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL_MTE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL_DPM_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL_VDM_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_PDS0_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL_PDS0_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL_PDS0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 -#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0 -/* Register EUR_CR_CLKGATECTL2 */ -#define EUR_CR_CLKGATECTL2 0x0004 -#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0 -#define EUR_CR_CLKGATECTL2_PBE_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_MASK 0x0000000CU -#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_SHIFT 2 -#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4 -#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U -#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6 -#define EUR_CR_CLKGATECTL2_USE0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8 -#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10 -#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_MADD0_CLKG_MASK 0x00003000U -#define EUR_CR_CLKGATECTL2_MADD0_CLKG_SHIFT 12 -#define EUR_CR_CLKGATECTL2_MADD0_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U -#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14 -#define EUR_CR_CLKGATECTL2_USE1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16 -#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18 -#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_MADD1_CLKG_MASK 0x00300000U -#define EUR_CR_CLKGATECTL2_MADD1_CLKG_SHIFT 20 -#define EUR_CR_CLKGATECTL2_MADD1_CLKG_SIGNED 0 -#define EUR_CR_CLKGATECTL2_PDS1_CLKG_MASK 0x00C00000U -#define EUR_CR_CLKGATECTL2_PDS1_CLKG_SHIFT 22 -#define EUR_CR_CLKGATECTL2_PDS1_CLKG_SIGNED 0 -/* Register EUR_CR_CLKGATESTATUS */ -#define EUR_CR_CLKGATESTATUS 0x0008 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0 -#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1 -#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2 -#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U -#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3 -#define EUR_CR_CLKGATESTATUS_TE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4 -#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5 -#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6 -#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_PDS0_CLKS_MASK 0x00000080U -#define EUR_CR_CLKGATESTATUS_PDS0_CLKS_SHIFT 7 -#define EUR_CR_CLKGATESTATUS_PDS0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8 -#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_MASK 0x00000200U -#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_SHIFT 9 -#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10 -#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11 -#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12 -#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13 -#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_MASK 0x00004000U -#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_SHIFT 14 -#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15 -#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16 -#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17 -#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_MASK 0x00040000U -#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_SHIFT 18 -#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_SIGNED 0 -#define EUR_CR_CLKGATESTATUS_PDS1_CLKS_MASK 0x00080000U -#define EUR_CR_CLKGATESTATUS_PDS1_CLKS_SHIFT 19 -#define EUR_CR_CLKGATESTATUS_PDS1_CLKS_SIGNED 0 -/* Register EUR_CR_CLKGATECTLOVR */ -#define EUR_CR_CLKGATECTLOVR 0x000C -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 -#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2 -#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4 -#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6 -#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8 -#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10 -#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12 -#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SIGNED 0 -#define EUR_CR_CLKGATECTLOVR_PDS0_CLKO_MASK 0x0000C000U -#define EUR_CR_CLKGATECTLOVR_PDS0_CLKO_SHIFT 14 -#define EUR_CR_CLKGATECTLOVR_PDS0_CLKO_SIGNED 0 -/* Register EUR_CR_CORE_ID */ -#define EUR_CR_CORE_ID 0x001C -#define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU -#define EUR_CR_CORE_ID_CONFIG_SHIFT 0 -#define EUR_CR_CORE_ID_CONFIG_SIGNED 0 -#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U -#define EUR_CR_CORE_ID_ID_SHIFT 16 -#define EUR_CR_CORE_ID_ID_SIGNED 0 -/* Register EUR_CR_CORE_REVISION */ -#define EUR_CR_CORE_REVISION 0x0020 -#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU -#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 -#define EUR_CR_CORE_REVISION_MAINTENANCE_SIGNED 0 -#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U -#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8 -#define EUR_CR_CORE_REVISION_MINOR_SIGNED 0 -#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U -#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 -#define EUR_CR_CORE_REVISION_MAJOR_SIGNED 0 -#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U -#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 -#define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0 -/* Register EUR_CR_DESIGNER_REV_FIELD1 */ -#define EUR_CR_DESIGNER_REV_FIELD1 0x0024 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 -#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0 -/* Register EUR_CR_DESIGNER_REV_FIELD2 */ -#define EUR_CR_DESIGNER_REV_FIELD2 0x002C -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 -#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0 -/* Register EUR_CR_SOFT_RESET */ -#define EUR_CR_SOFT_RESET 0x0080 -#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U -#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 -#define EUR_CR_SOFT_RESET_BIF_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000002U -#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 1 -#define EUR_CR_SOFT_RESET_DPM_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00000004U -#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 2 -#define EUR_CR_SOFT_RESET_TA_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00000008U -#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 3 -#define EUR_CR_SOFT_RESET_USE_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000010U -#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 4 -#define EUR_CR_SOFT_RESET_ISP_RESET_SIGNED 0 -#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000020U -#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 5 -#define EUR_CR_SOFT_RESET_TSP_RESET_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_ENABLE2 */ -#define EUR_CR_EVENT_HOST_ENABLE2 0x0110 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SHIFT 15 -#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_VDM_CONTEXT_LOAD_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_ENABLE2_VDM_CONTEXT_LOAD_SHIFT 14 -#define EUR_CR_EVENT_HOST_ENABLE2_VDM_CONTEXT_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_VDM_TASK_KICKED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_ENABLE2_VDM_TASK_KICKED_SHIFT 13 -#define EUR_CR_EVENT_HOST_ENABLE2_VDM_TASK_KICKED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_OTPM_MEM_CLEARED_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_ENABLE2_OTPM_MEM_CLEARED_SHIFT 12 -#define EUR_CR_EVENT_HOST_ENABLE2_OTPM_MEM_CLEARED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_OTPM_FLUSHED_INV_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE2_OTPM_FLUSHED_INV_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE2_OTPM_FLUSHED_INV_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_GSG_FLUSHED_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE2_GSG_FLUSHED_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE2_GSG_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_GSG_LOADED_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE2_GSG_LOADED_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE2_GSG_LOADED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_CLEAR2 */ -#define EUR_CR_EVENT_HOST_CLEAR2 0x0114 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SHIFT 15 -#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_VDM_CONTEXT_LOAD_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_CLEAR2_VDM_CONTEXT_LOAD_SHIFT 14 -#define EUR_CR_EVENT_HOST_CLEAR2_VDM_CONTEXT_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_VDM_TASK_KICKED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_CLEAR2_VDM_TASK_KICKED_SHIFT 13 -#define EUR_CR_EVENT_HOST_CLEAR2_VDM_TASK_KICKED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_OTPM_MEM_CLEARED_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_CLEAR2_OTPM_MEM_CLEARED_SHIFT 12 -#define EUR_CR_EVENT_HOST_CLEAR2_OTPM_MEM_CLEARED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_OTPM_FLUSHED_INV_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR2_OTPM_FLUSHED_INV_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR2_OTPM_FLUSHED_INV_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_GSG_FLUSHED_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR2_GSG_FLUSHED_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR2_GSG_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_GSG_LOADED_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR2_GSG_LOADED_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR2_GSG_LOADED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_STATUS2 */ -#define EUR_CR_EVENT_STATUS2 0x0118 -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_MASK 0x00008000U -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SHIFT 15 -#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_VDM_CONTEXT_LOAD_MASK 0x00004000U -#define EUR_CR_EVENT_STATUS2_VDM_CONTEXT_LOAD_SHIFT 14 -#define EUR_CR_EVENT_STATUS2_VDM_CONTEXT_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_VDM_TASK_KICKED_MASK 0x00002000U -#define EUR_CR_EVENT_STATUS2_VDM_TASK_KICKED_SHIFT 13 -#define EUR_CR_EVENT_STATUS2_VDM_TASK_KICKED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_OTPM_MEM_CLEARED_MASK 0x00001000U -#define EUR_CR_EVENT_STATUS2_OTPM_MEM_CLEARED_SHIFT 12 -#define EUR_CR_EVENT_STATUS2_OTPM_MEM_CLEARED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_OTPM_FLUSHED_INV_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS2_OTPM_FLUSHED_INV_SHIFT 11 -#define EUR_CR_EVENT_STATUS2_OTPM_FLUSHED_INV_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SHIFT 10 -#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_GSG_FLUSHED_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS2_GSG_FLUSHED_SHIFT 9 -#define EUR_CR_EVENT_STATUS2_GSG_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_GSG_LOADED_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS2_GSG_LOADED_SHIFT 8 -#define EUR_CR_EVENT_STATUS2_GSG_LOADED_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 7 -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 6 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 5 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_SHIFT 3 -#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_SHIFT 2 -#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 -#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0 -/* Register EUR_CR_EVENT_STATUS */ -#define EUR_CR_EVENT_STATUS 0x012C -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 -#define EUR_CR_EVENT_STATUS_TIMER_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_STATUS_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_STATUS_ISP2_ZLS_CSW_FINISHED_MASK 0x00200000U -#define EUR_CR_EVENT_STATUS_ISP2_ZLS_CSW_FINISHED_SHIFT 21 -#define EUR_CR_EVENT_STATUS_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_STATUS_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_SIGNED 0 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_STATUS_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_STATUS_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_STATUS_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_ENABLE */ -#define EUR_CR_EVENT_HOST_ENABLE 0x0130 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_ISP2_ZLS_CSW_FINISHED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP2_ZLS_CSW_FINISHED_SHIFT 21 -#define EUR_CR_EVENT_HOST_ENABLE_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_EVENT_HOST_CLEAR */ -#define EUR_CR_EVENT_HOST_CLEAR 0x0134 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 -#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 -#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26 -#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_ISP2_ZLS_CSW_FINISHED_MASK 0x00200000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP2_ZLS_CSW_FINISHED_SHIFT 21 -#define EUR_CR_EVENT_HOST_CLEAR_ISP2_ZLS_CSW_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19 -#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18 -#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_MASK 0x00010000U -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_SHIFT 16 -#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15 -#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14 -#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13 -#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12 -#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10 -#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SIGNED 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 -#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0 -/* Register EUR_CR_TIMER */ -#define EUR_CR_TIMER 0x0144 -#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU -#define EUR_CR_TIMER_VALUE_SHIFT 0 -#define EUR_CR_TIMER_VALUE_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_0 */ -#define EUR_CR_USE_CODE_BASE_0 0x0A0C -#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_1 */ -#define EUR_CR_USE_CODE_BASE_1 0x0A10 -#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_2 */ -#define EUR_CR_USE_CODE_BASE_2 0x0A14 -#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_3 */ -#define EUR_CR_USE_CODE_BASE_3 0x0A18 -#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_4 */ -#define EUR_CR_USE_CODE_BASE_4 0x0A1C -#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_5 */ -#define EUR_CR_USE_CODE_BASE_5 0x0A20 -#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_6 */ -#define EUR_CR_USE_CODE_BASE_6 0x0A24 -#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_7 */ -#define EUR_CR_USE_CODE_BASE_7 0x0A28 -#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_8 */ -#define EUR_CR_USE_CODE_BASE_8 0x0A2C -#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_9 */ -#define EUR_CR_USE_CODE_BASE_9 0x0A30 -#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_10 */ -#define EUR_CR_USE_CODE_BASE_10 0x0A34 -#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_11 */ -#define EUR_CR_USE_CODE_BASE_11 0x0A38 -#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_12 */ -#define EUR_CR_USE_CODE_BASE_12 0x0A3C -#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_13 */ -#define EUR_CR_USE_CODE_BASE_13 0x0A40 -#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_14 */ -#define EUR_CR_USE_CODE_BASE_14 0x0A44 -#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0 -/* Register EUR_CR_USE_CODE_BASE_15 */ -#define EUR_CR_USE_CODE_BASE_15 0x0A48 -#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0 -/* Register EUR_CR_PDS_EXEC_BASE */ -#define EUR_CR_PDS_EXEC_BASE 0x0AB8 -#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20 -#define EUR_CR_PDS_EXEC_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_EVENT_KICKER */ -#define EUR_CR_EVENT_KICKER 0x0AC4 -#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 -#define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0 -/* Register EUR_CR_EVENT_KICK */ -#define EUR_CR_EVENT_KICK 0x0AC8 -#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_TIMER */ -#define EUR_CR_EVENT_TIMER 0x0ACC -#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U -#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 -#define EUR_CR_EVENT_TIMER_ENABLE_SIGNED 0 -#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU -#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 -#define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0 -/* Register EUR_CR_PDS_INV0 */ -#define EUR_CR_PDS_INV0 0x0AD0 -#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV0_DSC_SHIFT 0 -#define EUR_CR_PDS_INV0_DSC_SIGNED 0 -/* Register EUR_CR_PDS_INV1 */ -#define EUR_CR_PDS_INV1 0x0AD4 -#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV1_DSC_SHIFT 0 -#define EUR_CR_PDS_INV1_DSC_SIGNED 0 -/* Register EUR_CR_PDS_INV3 */ -#define EUR_CR_PDS_INV3 0x0AD8 -#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U -#define EUR_CR_PDS_INV3_DSC_SHIFT 0 -#define EUR_CR_PDS_INV3_DSC_SIGNED 0 -/* Register EUR_CR_PDS_INV_CSC */ -#define EUR_CR_PDS_INV_CSC 0x0AE0 -#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U -#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 -#define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0 -/* Register EUR_CR_EVENT_KICK1 */ -#define EUR_CR_EVENT_KICK1 0x0AE4 -#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU -#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK1_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_KICK2 */ -#define EUR_CR_EVENT_KICK2 0x0AE8 -#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK2_NOW_SIGNED 0 -/* Register EUR_CR_EVENT_KICK3 */ -#define EUR_CR_EVENT_KICK3 0x0AEC -#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U -#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0 -#define EUR_CR_EVENT_KICK3_NOW_SIGNED 0 -/* Register EUR_CR_BIF_CTRL */ -#define EUR_CR_BIF_CTRL 0x0C00 -#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U -#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 -#define EUR_CR_BIF_CTRL_NOREORDER_SIGNED 0 -#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U -#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1 -#define EUR_CR_BIF_CTRL_PAUSE_SIGNED 0 -#define EUR_CR_BIF_CTRL_FLUSH_MASK 0x00000004U -#define EUR_CR_BIF_CTRL_FLUSH_SHIFT 2 -#define EUR_CR_BIF_CTRL_FLUSH_SIGNED 0 -#define EUR_CR_BIF_CTRL_INVALDC_MASK 0x00000008U -#define EUR_CR_BIF_CTRL_INVALDC_SHIFT 3 -#define EUR_CR_BIF_CTRL_INVALDC_SIGNED 0 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4 -#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_MASK 0x00000100U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_SHIFT 8 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00000800U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 11 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00001000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 12 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00002000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 13 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00004000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 14 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SIGNED 0 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_MASK 0x00008000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_SHIFT 15 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_SIGNED 0 -/* Register EUR_CR_BIF_INT_STAT */ -#define EUR_CR_BIF_INT_STAT 0x0C04 -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x0000FFFFU -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0 -#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SIGNED 0 -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK 0x00070000U -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SHIFT 16 -#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SIGNED 0 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19 -#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0 -/* Register EUR_CR_BIF_FAULT */ -#define EUR_CR_BIF_FAULT 0x0C08 -#define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU -#define EUR_CR_BIF_FAULT_CID_SHIFT 0 -#define EUR_CR_BIF_FAULT_CID_SIGNED 0 -#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U -#define EUR_CR_BIF_FAULT_SB_SHIFT 4 -#define EUR_CR_BIF_FAULT_SB_SIGNED 0 -#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 -#define EUR_CR_BIF_FAULT_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_TILE0 */ -#define EUR_CR_BIF_TILE0 0x0C0C -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE0_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE0_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE1 */ -#define EUR_CR_BIF_TILE1 0x0C10 -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE1_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE1_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE2 */ -#define EUR_CR_BIF_TILE2 0x0C14 -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE2_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE2_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE3 */ -#define EUR_CR_BIF_TILE3 0x0C18 -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE3_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE3_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE4 */ -#define EUR_CR_BIF_TILE4 0x0C1C -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE4_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE4_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE5 */ -#define EUR_CR_BIF_TILE5 0x0C20 -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE5_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE5_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE6 */ -#define EUR_CR_BIF_TILE6 0x0C24 -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE6_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE6_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE7 */ -#define EUR_CR_BIF_TILE7 0x0C28 -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE7_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE7_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE8 */ -#define EUR_CR_BIF_TILE8 0x0C2C -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE8_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE8_CFG_SIGNED 0 -/* Register EUR_CR_BIF_TILE9 */ -#define EUR_CR_BIF_TILE9 0x0C30 -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SIGNED 0 -#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE9_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE9_CFG_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE1 */ -#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38 -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE2 */ -#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE3 */ -#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40 -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE4 */ -#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44 -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE5 */ -#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48 -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE6 */ -#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE7 */ -#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50 -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE8 */ -#define EUR_CR_BIF_DIR_LIST_BASE8 0x0C54 -#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE9 */ -#define EUR_CR_BIF_DIR_LIST_BASE9 0x0C58 -#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE10 */ -#define EUR_CR_BIF_DIR_LIST_BASE10 0x0C5C -#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE11 */ -#define EUR_CR_BIF_DIR_LIST_BASE11 0x0C60 -#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE12 */ -#define EUR_CR_BIF_DIR_LIST_BASE12 0x0C64 -#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE13 */ -#define EUR_CR_BIF_DIR_LIST_BASE13 0x0C68 -#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE14 */ -#define EUR_CR_BIF_DIR_LIST_BASE14 0x0C6C -#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE15 */ -#define EUR_CR_BIF_DIR_LIST_BASE15 0x0C70 -#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_BANK_SET */ -#define EUR_CR_BIF_BANK_SET 0x0C74 -#define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U -#define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0 -#define EUR_CR_BIF_BANK_SET_SELECT_2D_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_3D_MASK 0x0000000CU -#define EUR_CR_BIF_BANK_SET_SELECT_3D_SHIFT 2 -#define EUR_CR_BIF_BANK_SET_SELECT_3D_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_MASK 0x00000010U -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SHIFT 4 -#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_TA_MASK 0x000000C0U -#define EUR_CR_BIF_BANK_SET_SELECT_TA_SHIFT 6 -#define EUR_CR_BIF_BANK_SET_SELECT_TA_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_MASK 0x00000100U -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SHIFT 8 -#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9 -#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0 -/* Register EUR_CR_BIF_BANK0 */ -#define EUR_CR_BIF_BANK0 0x0C78 -#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK0_INDEX_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK0_INDEX_TA_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_HOST_MASK 0x00000F00U -#define EUR_CR_BIF_BANK0_INDEX_HOST_SHIFT 8 -#define EUR_CR_BIF_BANK0_INDEX_HOST_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK0_INDEX_3D_SIGNED 0 -#define EUR_CR_BIF_BANK0_INDEX_2D_MASK 0x000F0000U -#define EUR_CR_BIF_BANK0_INDEX_2D_SHIFT 16 -#define EUR_CR_BIF_BANK0_INDEX_2D_SIGNED 0 -/* Register EUR_CR_BIF_BANK1 */ -#define EUR_CR_BIF_BANK1 0x0C7C -#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK1_INDEX_EDM_SIGNED 0 -#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK1_INDEX_TA_SIGNED 0 -#define EUR_CR_BIF_BANK1_INDEX_HOST_MASK 0x00000F00U -#define EUR_CR_BIF_BANK1_INDEX_HOST_SHIFT 8 -#define EUR_CR_BIF_BANK1_INDEX_HOST_SIGNED 0 -#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0 -#define EUR_CR_BIF_BANK1_INDEX_2D_MASK 0x000F0000U -#define EUR_CR_BIF_BANK1_INDEX_2D_SHIFT 16 -#define EUR_CR_BIF_BANK1_INDEX_2D_SIGNED 0 -/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ -#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFFF00U -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 8 -#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_TA_REQ_BASE */ -#define EUR_CR_BIF_TA_REQ_BASE 0x0C90 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_MEM_REQ_STAT */ -#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000007FFU -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 -#define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0 -/* Register EUR_CR_BIF_3D_REQ_BASE */ -#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_ZLS_REQ_BASE */ -#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0 -/* Register EUR_CR_BIF_BANK_STATUS */ -#define EUR_CR_BIF_BANK_STATUS 0x0CB4 -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0 -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SIGNED 0 -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0 -/* Register EUR_CR_BIF_36BIT_ADDRESSING */ -#define EUR_CR_BIF_36BIT_ADDRESSING 0x0CCC -#define EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK 0x00000001U -#define EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_SHIFT 0 -#define EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_SIGNED 0 -/* Register EUR_CR_BIF_TILE0_ADDR_EXT */ -#define EUR_CR_BIF_TILE0_ADDR_EXT 0x0CD0 -#define EUR_CR_BIF_TILE0_ADDR_EXT_MIN_MASK 0x000000FFU -#define EUR_CR_BIF_TILE0_ADDR_EXT_MIN_SHIFT 0 -#define EUR_CR_BIF_TILE0_ADDR_EXT_MIN_SIGNED 0 -#define EUR_CR_BIF_TILE0_ADDR_EXT_MAX_MASK 0x0000FF00U -#define EUR_CR_BIF_TILE0_ADDR_EXT_MAX_SHIFT 8 -#define EUR_CR_BIF_TILE0_ADDR_EXT_MAX_SIGNED 0 -/* Register EUR_CR_BIF_TILE1_ADDR_EXT */ -#define EUR_CR_BIF_TILE1_ADDR_EXT 0x0CD4 -#define EUR_CR_BIF_TILE1_ADDR_EXT_MIN_MASK 0x000000FFU -#define EUR_CR_BIF_TILE1_ADDR_EXT_MIN_SHIFT 0 -#define EUR_CR_BIF_TILE1_ADDR_EXT_MIN_SIGNED 0 -#define EUR_CR_BIF_TILE1_ADDR_EXT_MAX_MASK 0x0000FF00U -#define EUR_CR_BIF_TILE1_ADDR_EXT_MAX_SHIFT 8 -#define EUR_CR_BIF_TILE1_ADDR_EXT_MAX_SIGNED 0 -/* Register EUR_CR_BIF_TILE2_ADDR_EXT */ -#define EUR_CR_BIF_TILE2_ADDR_EXT 0x0CD8 -#define EUR_CR_BIF_TILE2_ADDR_EXT_MIN_MASK 0x000000FFU -#define EUR_CR_BIF_TILE2_ADDR_EXT_MIN_SHIFT 0 -#define EUR_CR_BIF_TILE2_ADDR_EXT_MIN_SIGNED 0 -#define EUR_CR_BIF_TILE2_ADDR_EXT_MAX_MASK 0x0000FF00U -#define EUR_CR_BIF_TILE2_ADDR_EXT_MAX_SHIFT 8 -#define EUR_CR_BIF_TILE2_ADDR_EXT_MAX_SIGNED 0 -/* Register EUR_CR_BIF_TILE3_ADDR_EXT */ -#define EUR_CR_BIF_TILE3_ADDR_EXT 0x0CDC -#define EUR_CR_BIF_TILE3_ADDR_EXT_MIN_MASK 0x000000FFU -#define EUR_CR_BIF_TILE3_ADDR_EXT_MIN_SHIFT 0 -#define EUR_CR_BIF_TILE3_ADDR_EXT_MIN_SIGNED 0 -#define EUR_CR_BIF_TILE3_ADDR_EXT_MAX_MASK 0x0000FF00U -#define EUR_CR_BIF_TILE3_ADDR_EXT_MAX_SHIFT 8 -#define EUR_CR_BIF_TILE3_ADDR_EXT_MAX_SIGNED 0 -/* Register EUR_CR_BIF_TILE4_ADDR_EXT */ -#define EUR_CR_BIF_TILE4_ADDR_EXT 0x0CE0 -#define EUR_CR_BIF_TILE4_ADDR_EXT_MIN_MASK 0x000000FFU -#define EUR_CR_BIF_TILE4_ADDR_EXT_MIN_SHIFT 0 -#define EUR_CR_BIF_TILE4_ADDR_EXT_MIN_SIGNED 0 -#define EUR_CR_BIF_TILE4_ADDR_EXT_MAX_MASK 0x0000FF00U -#define EUR_CR_BIF_TILE4_ADDR_EXT_MAX_SHIFT 8 -#define EUR_CR_BIF_TILE4_ADDR_EXT_MAX_SIGNED 0 -/* Register EUR_CR_BIF_TILE5_ADDR_EXT */ -#define EUR_CR_BIF_TILE5_ADDR_EXT 0x0CE4 -#define EUR_CR_BIF_TILE5_ADDR_EXT_MIN_MASK 0x000000FFU -#define EUR_CR_BIF_TILE5_ADDR_EXT_MIN_SHIFT 0 -#define EUR_CR_BIF_TILE5_ADDR_EXT_MIN_SIGNED 0 -#define EUR_CR_BIF_TILE5_ADDR_EXT_MAX_MASK 0x0000FF00U -#define EUR_CR_BIF_TILE5_ADDR_EXT_MAX_SHIFT 8 -#define EUR_CR_BIF_TILE5_ADDR_EXT_MAX_SIGNED 0 -/* Register EUR_CR_BIF_TILE6_ADDR_EXT */ -#define EUR_CR_BIF_TILE6_ADDR_EXT 0x0CE8 -#define EUR_CR_BIF_TILE6_ADDR_EXT_MIN_MASK 0x000000FFU -#define EUR_CR_BIF_TILE6_ADDR_EXT_MIN_SHIFT 0 -#define EUR_CR_BIF_TILE6_ADDR_EXT_MIN_SIGNED 0 -#define EUR_CR_BIF_TILE6_ADDR_EXT_MAX_MASK 0x0000FF00U -#define EUR_CR_BIF_TILE6_ADDR_EXT_MAX_SHIFT 8 -#define EUR_CR_BIF_TILE6_ADDR_EXT_MAX_SIGNED 0 -/* Register EUR_CR_BIF_TILE7_ADDR_EXT */ -#define EUR_CR_BIF_TILE7_ADDR_EXT 0x0CEC -#define EUR_CR_BIF_TILE7_ADDR_EXT_MIN_MASK 0x000000FFU -#define EUR_CR_BIF_TILE7_ADDR_EXT_MIN_SHIFT 0 -#define EUR_CR_BIF_TILE7_ADDR_EXT_MIN_SIGNED 0 -#define EUR_CR_BIF_TILE7_ADDR_EXT_MAX_MASK 0x0000FF00U -#define EUR_CR_BIF_TILE7_ADDR_EXT_MAX_SHIFT 8 -#define EUR_CR_BIF_TILE7_ADDR_EXT_MAX_SIGNED 0 -/* Register EUR_CR_BIF_TILE8_ADDR_EXT */ -#define EUR_CR_BIF_TILE8_ADDR_EXT 0x0CF0 -#define EUR_CR_BIF_TILE8_ADDR_EXT_MIN_MASK 0x000000FFU -#define EUR_CR_BIF_TILE8_ADDR_EXT_MIN_SHIFT 0 -#define EUR_CR_BIF_TILE8_ADDR_EXT_MIN_SIGNED 0 -#define EUR_CR_BIF_TILE8_ADDR_EXT_MAX_MASK 0x0000FF00U -#define EUR_CR_BIF_TILE8_ADDR_EXT_MAX_SHIFT 8 -#define EUR_CR_BIF_TILE8_ADDR_EXT_MAX_SIGNED 0 -/* Register EUR_CR_BIF_TILE9_ADDR_EXT */ -#define EUR_CR_BIF_TILE9_ADDR_EXT 0x0CF4 -#define EUR_CR_BIF_TILE9_ADDR_EXT_MIN_MASK 0x000000FFU -#define EUR_CR_BIF_TILE9_ADDR_EXT_MIN_SHIFT 0 -#define EUR_CR_BIF_TILE9_ADDR_EXT_MIN_SIGNED 0 -#define EUR_CR_BIF_TILE9_ADDR_EXT_MAX_MASK 0x0000FF00U -#define EUR_CR_BIF_TILE9_ADDR_EXT_MAX_SHIFT 8 -#define EUR_CR_BIF_TILE9_ADDR_EXT_MAX_SIGNED 0 -/* Register EUR_CR_BIF_CTRL_RDATA */ -#define EUR_CR_BIF_CTRL_RDATA 0x0CF8 -#define EUR_CR_BIF_CTRL_RDATA_LIMIT_MASK 0x000003FFU -#define EUR_CR_BIF_CTRL_RDATA_LIMIT_SHIFT 0 -#define EUR_CR_BIF_CTRL_RDATA_LIMIT_SIGNED 0 -/* Table EUR_CR_USE_CODE_BASE */ -/* Register EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) -#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x01FFFFFFU -#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_ADDR_SIGNED 0 -#define EUR_CR_USE_CODE_BASE_DM_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_SHIFT 25 -#define EUR_CR_USE_CODE_BASE_DM_SIGNED 0 -/* Number of entries in table EUR_CR_USE_CODE_BASE */ -#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 -#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 - -#endif /* _SGX545DEFS_KM_H_ */ - diff --git a/pvr-source/services4/srvkm/hwdefs/sgxdefs.h b/pvr-source/services4/srvkm/hwdefs/sgxdefs.h deleted file mode 100755 index ed24647..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgxdefs.h +++ /dev/null @@ -1,112 +0,0 @@ -/*************************************************************************/ /*! -@Title SGX hw definitions -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGXDEFS_H_ -#define _SGXDEFS_H_ - -#include "sgxerrata.h" -#include "sgxfeaturedefs.h" - -#if defined(SGX520) -#include "sgx520defs.h" -#else -#if defined(SGX530) -#include "sgx530defs.h" -#else -#if defined(SGX535) -#include "sgx535defs.h" -#else -#if defined(SGX535_V1_1) -#include "sgx535defs.h" -#else -#if defined(SGX540) -#include "sgx540defs.h" -#else -#if defined(SGX543) -#if defined(FIX_HW_BRN_29954) -#include "sgx543_v1.164defs.h" -#else -#include "sgx543defs.h" -#endif -#else -#if defined(SGX544) -#include "sgx544defs.h" -#else -#if defined(SGX545) -#include "sgx545defs.h" -#else -#if defined(SGX531) -#include "sgx531defs.h" -#else -#if defined(SGX554) -#include "sgx554defs.h" -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif - -#if defined(SGX_FEATURE_MP) -#if defined(SGX554) -#include "sgxmpplusdefs.h" -#else -#include "sgxmpdefs.h" -#endif /* SGX554 */ -#else /* SGX_FEATURE_MP */ -#if defined(SGX_FEATURE_SYSTEM_CACHE) -#include "mnemedefs.h" -#endif -#endif /* SGX_FEATURE_MP */ - -/***************************************************************************** - Core specific defines. -*****************************************************************************/ - -#endif /* _SGXDEFS_H_ */ - -/***************************************************************************** - End of file (sgxdefs.h) -*****************************************************************************/ diff --git a/pvr-source/services4/srvkm/hwdefs/sgxerrata.h b/pvr-source/services4/srvkm/hwdefs/sgxerrata.h deleted file mode 100755 index 437fbc6..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgxerrata.h +++ /dev/null @@ -1,495 +0,0 @@ -/*************************************************************************/ /*! -@Title SGX HW errata definitions -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@Description Specifies associations between SGX core revisions - and SW workarounds required to fix HW errata that exist - in specific core revisions -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ -#ifndef _SGXERRATA_KM_H_ -#define _SGXERRATA_KM_H_ - -/* ignore warnings about unrecognised preprocessing directives in conditional inclusion directives */ -/* PRQA S 3115 ++ */ - -#if defined(SGX520) && !defined(SGX_CORE_DEFINED) - /* define the _current_ SGX520 RTL head revision */ - #define SGX_CORE_REV_HEAD 0 - #if defined(USE_SGX_CORE_REV_HEAD) - /* build config selects Core Revision to be the Head */ - #define SGX_CORE_REV SGX_CORE_REV_HEAD - #endif - - #if SGX_CORE_REV == 111 - #else - #if SGX_CORE_REV == SGX_CORE_REV_HEAD - /* RTL head - no BRNs to apply */ - #else - #error "sgxerrata.h: SGX520 Core Revision unspecified" - #endif - #endif - /* signal that the Core Version has a valid definition */ - #define SGX_CORE_DEFINED -#endif - -#if defined(SGX530) && !defined(SGX_CORE_DEFINED) - /* define the _current_ SGX530 RTL head revision */ - #define SGX_CORE_REV_HEAD 0 - #if defined(USE_SGX_CORE_REV_HEAD) - /* build config selects Core Revision to be the Head */ - #define SGX_CORE_REV SGX_CORE_REV_HEAD - #endif - - #if SGX_CORE_REV == 120 - #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ - #define FIX_HW_BRN_28889/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == 121 - #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ - #define FIX_HW_BRN_28889/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == 125 - #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ - #define FIX_HW_BRN_28889/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == 130 - #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ - #define FIX_HW_BRN_28889/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == SGX_CORE_REV_HEAD - /* RTL head - no BRNs to apply */ - #else - #error "sgxerrata.h: SGX530 Core Revision unspecified" - #endif - #endif - #endif -#endif - #endif - /* signal that the Core Version has a valid definition */ - #define SGX_CORE_DEFINED -#endif - -#if defined(SGX531) && !defined(SGX_CORE_DEFINED) - /* define the _current_ SGX531 RTL head revision */ - #define SGX_CORE_REV_HEAD 0 - #if defined(USE_SGX_CORE_REV_HEAD) - /* build config selects Core Revision to be the Head */ - #define SGX_CORE_REV SGX_CORE_REV_HEAD - #endif - - #if SGX_CORE_REV == 101 - #define FIX_HW_BRN_26620/* Workaround in services (srvkm) */ - #define FIX_HW_BRN_28011/* Workaround in services (srvkm) */ - #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == 110 - #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == SGX_CORE_REV_HEAD - /* RTL head - no BRNs to apply */ - #else - #error "sgxerrata.h: SGX531 Core Revision unspecified" - #endif - #endif - #endif - /* signal that the Core Version has a valid definition */ - #define SGX_CORE_DEFINED -#endif - -#if (defined(SGX535) || defined(SGX535_V1_1)) && !defined(SGX_CORE_DEFINED) - /* define the _current_ SGX535 RTL head revision */ - #define SGX_CORE_REV_HEAD 0 - #if defined(USE_SGX_CORE_REV_HEAD) - /* build config selects Core Revision to be the Head */ - #define SGX_CORE_REV SGX_CORE_REV_HEAD - #endif - - #if SGX_CORE_REV == 121 - #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ - #define FIX_HW_BRN_23944/* Workaround in code (services) */ - #define FIX_HW_BRN_23410/* Workaround in code (services) and ucode */ - #else - #if SGX_CORE_REV == 126 - #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ - #else - #if SGX_CORE_REV == SGX_CORE_REV_HEAD - /* RTL head - no BRNs to apply */ - #else - #error "sgxerrata.h: SGX535 Core Revision unspecified" - - #endif - #endif - #endif - /* signal that the Core Version has a valid definition */ - #define SGX_CORE_DEFINED -#endif - -#if defined(SGX540) && !defined(SGX_CORE_DEFINED) - /* define the _current_ SGX540 RTL head revision */ - #define SGX_CORE_REV_HEAD 0 - #if defined(USE_SGX_CORE_REV_HEAD) - /* build config selects Core Revision to be the Head */ - #define SGX_CORE_REV SGX_CORE_REV_HEAD - #endif - - #if SGX_CORE_REV == 101 - #define FIX_HW_BRN_25499/* Workaround in sgx featuredefs */ - #define FIX_HW_BRN_25503/* Workaround in code (services) */ - #define FIX_HW_BRN_26620/* Workaround in services (srvkm) */ - #define FIX_HW_BRN_28011/* Workaround in services (srvkm) */ - #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == 110 - #define FIX_HW_BRN_25503/* Workaround in code (services) */ - #define FIX_HW_BRN_26620/* Workaround in services (srvkm) */ - #define FIX_HW_BRN_28011/* Workaround in services (srvkm) */ - #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == 120 - #define FIX_HW_BRN_26620/* Workaround in services (srvkm) */ - #define FIX_HW_BRN_28011/* Workaround in services (srvkm) */ - #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == 121 - #define FIX_HW_BRN_28011/* Workaround in services (srvkm) */ - #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == 130 - #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ - #else - #if SGX_CORE_REV == SGX_CORE_REV_HEAD - /* RTL head - no BRNs to apply */ - #else - #error "sgxerrata.h: SGX540 Core Revision unspecified" - #endif - #endif - #endif - #endif - #endif - #endif - /* signal that the Core Version has a valid definition */ - #define SGX_CORE_DEFINED -#endif - - -#if defined(SGX543) && !defined(SGX_CORE_DEFINED) - /* define the _current_ SGX543 RTL head revision */ - #define SGX_CORE_REV_HEAD 0 - #if defined(USE_SGX_CORE_REV_HEAD) - /* build config selects Core Revision to be the Head */ - #define SGX_CORE_REV SGX_CORE_REV_HEAD - #endif - - #if SGX_CORE_REV == 122 - #define FIX_HW_BRN_29954/* turns off regbank split feature */ - #define FIX_HW_BRN_29997/* workaround in services */ - #define FIX_HW_BRN_30954/* workaround in services */ - #define FIX_HW_BRN_31093/* workaround in services */ - #define FIX_HW_BRN_31195/* workaround in services */ - #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ - #define FIX_HW_BRN_31278/* disabled prefetching in MMU */ - #define FIX_HW_BRN_31542/* workaround in uKernel and Services */ - #define FIX_HW_BRN_31620/* workaround in services */ - #define FIX_HW_BRN_31780/* workaround in uKernel */ - #define FIX_HW_BRN_32044 /* workaround in uKernel, services and client drivers */ - #define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */ - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_33920/* workaround in ukernel */ - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - /* add BRNs here */ - #else - #if SGX_CORE_REV == 1221 - #define FIX_HW_BRN_29954/* turns off regbank split feature */ - #define FIX_HW_BRN_31195/* workaround in services */ - #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ - #define FIX_HW_BRN_31278/* disabled prefetching in MMU */ - #define FIX_HW_BRN_31542/* workaround in uKernel and Services */ - #define FIX_HW_BRN_31671/* workaround in uKernel */ - #define FIX_HW_BRN_31780/* workaround in uKernel */ - #define FIX_HW_BRN_32044/* workaround in uKernel, services and client drivers */ - #define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */ - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_33920/* workaround in ukernel */ - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - /* add BRNs here */ - #else - #if SGX_CORE_REV == 141 - #define FIX_HW_BRN_29954/* turns off regbank split feature */ - #define FIX_HW_BRN_31671 /* workaround in uKernel */ - #define FIX_HW_BRN_31780/* workaround in uKernel */ - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - /* add BRNs here */ - #else - #if SGX_CORE_REV == 142 - #define FIX_HW_BRN_29954/* turns off regbank split feature */ - #define FIX_HW_BRN_31671 /* workaround in uKernel */ - #define FIX_HW_BRN_31780/* workaround in uKernel */ - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - /* add BRNs here */ - #else - #if SGX_CORE_REV == 2111 - #define FIX_HW_BRN_30982 /* workaround in uKernel and services */ - #define FIX_HW_BRN_31093/* workaround in services */ - #define FIX_HW_BRN_31195/* workaround in services */ - #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ - #define FIX_HW_BRN_31278/* disabled prefetching in MMU */ - #define FIX_HW_BRN_31542/* workaround in uKernel and Services */ - #define FIX_HW_BRN_31620/* workaround in services */ - #define FIX_HW_BRN_31780/* workaround in uKernel */ - #define FIX_HW_BRN_32044 /* workaround in uKernel, services and client drivers */ - #define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */ - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_33920/* workaround in ukernel */ - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - /* add BRNs here */ - #else - #if SGX_CORE_REV == 213 - #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ - #define FIX_HW_BRN_31671 /* workaround in uKernel */ - #define FIX_HW_BRN_31780/* workaround in uKernel */ - #define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */ - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_33920/* workaround in ukernel */ - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - /* add BRNs here */ - #else - #if SGX_CORE_REV == 216 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - #else - #if SGX_CORE_REV == 302 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - #else - #if SGX_CORE_REV == 303 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - #else - #if SGX_CORE_REV == SGX_CORE_REV_HEAD - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #else - #error "sgxerrata.h: SGX543 Core Revision unspecified" - #endif - #endif - #endif - #endif - #endif - #endif - #endif - #endif - #endif - #endif - /* signal that the Core Version has a valid definition */ - #define SGX_CORE_DEFINED -#endif - -#if defined(SGX544) && !defined(SGX_CORE_DEFINED) - /* define the _current_ SGX544 RTL head revision */ - #define SGX_CORE_REV_HEAD 0 - #if defined(USE_SGX_CORE_REV_HEAD) - /* build config selects Core Revision to be the Head */ - #define SGX_CORE_REV SGX_CORE_REV_HEAD - #endif - - #if SGX_CORE_REV == 104 - #define FIX_HW_BRN_29954/* turns off regbank split feature */ - #define FIX_HW_BRN_31093/* workaround in services */ - #define FIX_HW_BRN_31195/* workaround in services */ - #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ - #define FIX_HW_BRN_31278/* disabled prefetching in MMU */ - #define FIX_HW_BRN_31542 /* workaround in uKernel and Services */ - #define FIX_HW_BRN_31620/* workaround in services */ - #define FIX_HW_BRN_31671 /* workaround in uKernel */ - #define FIX_HW_BRN_31780/* workaround in uKernel */ - #define FIX_HW_BRN_32044 /* workaround in uKernel, services and client drivers */ - #define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */ - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_33920/* workaround in ukernel */ - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - #else - #if SGX_CORE_REV == 105 - #define FIX_HW_BRN_31780/* workaround in uKernel */ - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_33920/* workaround in ukernel */ - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - #else - #if SGX_CORE_REV == 112 - #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ - #define FIX_HW_BRN_33920/* workaround in ukernel */ - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - #else - #if SGX_CORE_REV == 114 - #define FIX_HW_BRN_31780/* workaround in uKernel */ - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - #else - #if SGX_CORE_REV == 115 - #define FIX_HW_BRN_31780/* workaround in uKernel */ - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - #else - #if SGX_CORE_REV == 116 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel */ - #endif - //FIXME: This causes DMM/EMIF lockup - //#define FIX_HW_BRN_33809/* workaround in kernel (enable burst combiner) */ - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - #else - #if SGX_CORE_REV == SGX_CORE_REV_HEAD - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #else - #error "sgxerrata.h: SGX544 Core Revision unspecified" - #endif - #endif - #endif - #endif - #endif - #endif - #endif - /* signal that the Core Version has a valid definition */ - #define SGX_CORE_DEFINED -#endif - -#if defined(SGX545) && !defined(SGX_CORE_DEFINED) - /* define the _current_ SGX545 RTL head revision */ - #define SGX_CORE_REV_HEAD 0 - #if defined(USE_SGX_CORE_REV_HEAD) - /* build config selects Core Revision to be the Head */ - #define SGX_CORE_REV SGX_CORE_REV_HEAD - #endif - - #if SGX_CORE_REV == 109 - #define FIX_HW_BRN_29702/* Workaround in services */ - #define FIX_HW_BRN_29823/* Workaround in services */ - #define FIX_HW_BRN_31939/* workaround in uKernel */ - #else - #if SGX_CORE_REV == 10131 - #else - #if SGX_CORE_REV == 1014 - #else - #if SGX_CORE_REV == 10141 - #else - #if SGX_CORE_REV == SGX_CORE_REV_HEAD - /* RTL head - no BRNs to apply */ - #else - #error "sgxerrata.h: SGX545 Core Revision unspecified" - #endif - #endif - #endif - #endif - #endif - /* signal that the Core Version has a valid definition */ - #define SGX_CORE_DEFINED -#endif - -#if defined(SGX554) && !defined(SGX_CORE_DEFINED) - /* define the _current_ SGX554 RTL head revision */ - #define SGX_CORE_REV_HEAD 0 - #if defined(USE_SGX_CORE_REV_HEAD) - /* build config selects Core Revision to be the Head */ - #define SGX_CORE_REV SGX_CORE_REV_HEAD - #endif - - #if SGX_CORE_REV == 1251 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ - /* add BRNs here */ - #else - #if SGX_CORE_REV == SGX_CORE_REV_HEAD - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657/* workaround in ukernel*/ - #endif - #else - #error "sgxerrata.h: SGX554 Core Revision unspecified" - #endif - #endif - /* signal that the Core Version has a valid definition */ - #define SGX_CORE_DEFINED -#endif - -#if !defined(SGX_CORE_DEFINED) -#if defined (__GNUC__) - #warning "sgxerrata.h: SGX Core Version unspecified" -#else - #pragma message("sgxerrata.h: SGX Core Version unspecified") -#endif -#endif - -/* restore warning */ -/* PRQA S 3115 -- */ - -#endif /* _SGXERRATA_KM_H_ */ - -/****************************************************************************** - End of file (sgxerrata.h) -******************************************************************************/ diff --git a/pvr-source/services4/srvkm/hwdefs/sgxfeaturedefs.h b/pvr-source/services4/srvkm/hwdefs/sgxfeaturedefs.h deleted file mode 100755 index 3e3a116..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgxfeaturedefs.h +++ /dev/null @@ -1,274 +0,0 @@ -/*************************************************************************/ /*! -@Title SGX fexture definitions -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ -#if defined(SGX520) - #define SGX_CORE_FRIENDLY_NAME "SGX520" - #define SGX_CORE_ID SGX_CORE_ID_520 - #define SGX_FEATURE_ADDRESS_SPACE_SIZE (28) - #define SGX_FEATURE_NUM_USE_PIPES (1) - #define SGX_FEATURE_AUTOCLOCKGATING -#else -#if defined(SGX530) - #define SGX_CORE_FRIENDLY_NAME "SGX530" - #define SGX_CORE_ID SGX_CORE_ID_530 - #define SGX_FEATURE_ADDRESS_SPACE_SIZE (28) - #define SGX_FEATURE_NUM_USE_PIPES (2) - #define SGX_FEATURE_AUTOCLOCKGATING -#else -#if defined(SGX531) - #define SGX_CORE_FRIENDLY_NAME "SGX531" - #define SGX_CORE_ID SGX_CORE_ID_531 - #define SGX_FEATURE_ADDRESS_SPACE_SIZE (28) - #define SGX_FEATURE_NUM_USE_PIPES (2) - #define SGX_FEATURE_AUTOCLOCKGATING - #define SGX_FEATURE_MULTI_EVENT_KICK -#else -#if defined(SGX535) - #define SGX_CORE_FRIENDLY_NAME "SGX535" - #define SGX_CORE_ID SGX_CORE_ID_535 - #define SGX_FEATURE_ADDRESS_SPACE_SIZE (32) - #define SGX_FEATURE_MULTIPLE_MEM_CONTEXTS - #define SGX_FEATURE_BIF_NUM_DIRLISTS (16) - #define SGX_FEATURE_2D_HARDWARE - #define SGX_FEATURE_NUM_USE_PIPES (2) - #define SGX_FEATURE_AUTOCLOCKGATING - #define SUPPORT_SGX_GENERAL_MAPPING_HEAP - #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE -#else -#if defined(SGX540) - #define SGX_CORE_FRIENDLY_NAME "SGX540" - #define SGX_CORE_ID SGX_CORE_ID_540 - #define SGX_FEATURE_ADDRESS_SPACE_SIZE (28) - #define SGX_FEATURE_NUM_USE_PIPES (4) - #define SGX_FEATURE_AUTOCLOCKGATING - #define SGX_FEATURE_MULTI_EVENT_KICK -#else -#if defined(SGX543) - #define SGX_CORE_FRIENDLY_NAME "SGX543" - #define SGX_CORE_ID SGX_CORE_ID_543 - #define SGX_FEATURE_USE_NO_INSTRUCTION_PAIRING - #define SGX_FEATURE_USE_UNLIMITED_PHASES - #define SGX_FEATURE_ADDRESS_SPACE_SIZE (32) - #define SGX_FEATURE_MULTIPLE_MEM_CONTEXTS - #define SGX_FEATURE_BIF_NUM_DIRLISTS (8) - #define SGX_FEATURE_NUM_USE_PIPES (4) - #define SGX_FEATURE_AUTOCLOCKGATING - #define SGX_FEATURE_MONOLITHIC_UKERNEL - #define SGX_FEATURE_MULTI_EVENT_KICK - #define SGX_FEATURE_DATA_BREAKPOINTS - #define SGX_FEATURE_PERPIPE_BKPT_REGS - #define SGX_FEATURE_PERPIPE_BKPT_REGS_NUMPIPES (2) - #define SGX_FEATURE_2D_HARDWARE - #define SGX_FEATURE_PTLA - #define SGX_FEATURE_EXTENDED_PERF_COUNTERS - #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) - #if defined(SGX_FEATURE_MP) - #define SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH - #endif - #define SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH - #define SGX_FEATURE_SW_ISP_CONTEXT_SWITCH - #endif -#else -#if defined(SGX544) - #define SGX_CORE_FRIENDLY_NAME "SGX544" - #define SGX_CORE_ID SGX_CORE_ID_544 - #define SGX_FEATURE_USE_NO_INSTRUCTION_PAIRING - #define SGX_FEATURE_USE_UNLIMITED_PHASES - #define SGX_FEATURE_ADDRESS_SPACE_SIZE (32) - #define SGX_FEATURE_MULTIPLE_MEM_CONTEXTS - #define SGX_FEATURE_BIF_NUM_DIRLISTS (8) - #define SGX_FEATURE_NUM_USE_PIPES (4) - #define SGX_FEATURE_AUTOCLOCKGATING - #define SGX_FEATURE_MONOLITHIC_UKERNEL - #define SGX_FEATURE_MULTI_EVENT_KICK -// #define SGX_FEATURE_DATA_BREAKPOINTS -// #define SGX_FEATURE_PERPIPE_BKPT_REGS -// #define SGX_FEATURE_PERPIPE_BKPT_REGS_NUMPIPES (2) -// #define SGX_FEATURE_2D_HARDWARE -// #define SGX_FEATURE_PTLA - #define SGX_FEATURE_EXTENDED_PERF_COUNTERS - #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) - #if defined(SGX_FEATURE_MP) - #define SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH - #define SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH - #endif - #define SGX_FEATURE_SW_ISP_CONTEXT_SWITCH - #endif -#else -#if defined(SGX545) - #define SGX_CORE_FRIENDLY_NAME "SGX545" - #define SGX_CORE_ID SGX_CORE_ID_545 - #define SGX_FEATURE_ADDRESS_SPACE_SIZE (32) - #define SGX_FEATURE_AUTOCLOCKGATING - #define SGX_FEATURE_USE_NO_INSTRUCTION_PAIRING - #define SGX_FEATURE_USE_UNLIMITED_PHASES - #define SGX_FEATURE_VOLUME_TEXTURES - #define SGX_FEATURE_HOST_ALLOC_FROM_DPM - #define SGX_FEATURE_MULTIPLE_MEM_CONTEXTS - #define SGX_FEATURE_BIF_NUM_DIRLISTS (16) - #define SGX_FEATURE_NUM_USE_PIPES (4) - #define SGX_FEATURE_TEXTURESTRIDE_EXTENSION - #define SGX_FEATURE_PDS_DATA_INTERLEAVE_2DWORDS - #define SGX_FEATURE_MONOLITHIC_UKERNEL - #define SGX_FEATURE_ZLS_EXTERNALZ - #define SGX_FEATURE_NUM_PDS_PIPES (2) - #define SGX_FEATURE_NATIVE_BACKWARD_BLIT - #define SGX_FEATURE_MAX_TA_RENDER_TARGETS (512) - #define SGX_FEATURE_SECONDARY_REQUIRES_USE_KICK - #define SGX_FEATURE_WRITEBACK_DCU - //FIXME: this is defined in the build config for now - //#define SGX_FEATURE_36BIT_MMU - #define SGX_FEATURE_BIF_WIDE_TILING_AND_4K_ADDRESS - #define SGX_FEATURE_MULTI_EVENT_KICK - #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) - #define SGX_FEATURE_SW_ISP_CONTEXT_SWITCH - #endif -#else -#if defined(SGX554) - #define SGX_CORE_FRIENDLY_NAME "SGX554" - #define SGX_CORE_ID SGX_CORE_ID_554 - #define SGX_FEATURE_USE_NO_INSTRUCTION_PAIRING - #define SGX_FEATURE_USE_UNLIMITED_PHASES - #define SGX_FEATURE_ADDRESS_SPACE_SIZE (32) - #define SGX_FEATURE_MULTIPLE_MEM_CONTEXTS - #define SGX_FEATURE_BIF_NUM_DIRLISTS (8) - #define SGX_FEATURE_NUM_USE_PIPES (8) - #define SGX_FEATURE_AUTOCLOCKGATING - #define SGX_FEATURE_MONOLITHIC_UKERNEL - #define SGX_FEATURE_MULTI_EVENT_KICK -// #define SGX_FEATURE_DATA_BREAKPOINTS -// #define SGX_FEATURE_PERPIPE_BKPT_REGS -// #define SGX_FEATURE_PERPIPE_BKPT_REGS_NUMPIPES (2) - #define SGX_FEATURE_2D_HARDWARE - #define SGX_FEATURE_PTLA - #define SGX_FEATURE_EXTENDED_PERF_COUNTERS - #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) - #if defined(SGX_FEATURE_MP) - #define SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH - #endif - #define SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH - #define SGX_FEATURE_SW_ISP_CONTEXT_SWITCH - #endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif - -#if defined(SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH) \ - || defined(SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH) -/* Enable the define so common code for HW VDMCS code is compiled */ -#define SGX_FEATURE_VDM_CONTEXT_SWITCH -#endif - -/* - 'switch-off' features if defined BRNs affect the feature -*/ - -#if defined(FIX_HW_BRN_27266) -#undef SGX_FEATURE_36BIT_MMU -#endif - -#if defined(FIX_HW_BRN_22934) \ - || defined(FIX_HW_BRN_25499) -#undef SGX_FEATURE_MULTI_EVENT_KICK -#endif - -#if defined(SGX_FEATURE_SYSTEM_CACHE) - #if defined(SGX_FEATURE_36BIT_MMU) - #error SGX_FEATURE_SYSTEM_CACHE is incompatible with SGX_FEATURE_36BIT_MMU - #endif - #if defined(FIX_HW_BRN_26620) && !defined(SGX_FEATURE_MULTI_EVENT_KICK) - #define SGX_BYPASS_SYSTEM_CACHE - #endif -#endif - -#if defined(FIX_HW_BRN_29954) -#undef SGX_FEATURE_PERPIPE_BKPT_REGS -#endif - -#if defined(FIX_HW_BRN_31620) -#undef SGX_FEATURE_MULTIPLE_MEM_CONTEXTS -#undef SGX_FEATURE_BIF_NUM_DIRLISTS -#endif - -/* - Derive other definitions: -*/ - -/* define default MP core count */ -#if defined(SGX_FEATURE_MP) -#if defined(SGX_FEATURE_MP_CORE_COUNT_TA) && defined(SGX_FEATURE_MP_CORE_COUNT_3D) -#if (SGX_FEATURE_MP_CORE_COUNT_TA > SGX_FEATURE_MP_CORE_COUNT_3D) -#error Number of TA cores larger than number of 3D cores not supported in current driver -#endif /* (SGX_FEATURE_MP_CORE_COUNT_TA > SGX_FEATURE_MP_CORE_COUNT_3D) */ -#else -#if defined(SGX_FEATURE_MP_CORE_COUNT) -#define SGX_FEATURE_MP_CORE_COUNT_TA (SGX_FEATURE_MP_CORE_COUNT) -#define SGX_FEATURE_MP_CORE_COUNT_3D (SGX_FEATURE_MP_CORE_COUNT) -#else -#error Either SGX_FEATURE_MP_CORE_COUNT or \ -both SGX_FEATURE_MP_CORE_COUNT_TA and SGX_FEATURE_MP_CORE_COUNT_3D \ -must be defined when SGX_FEATURE_MP is defined -#endif /* SGX_FEATURE_MP_CORE_COUNT */ -#endif /* defined(SGX_FEATURE_MP_CORE_COUNT_TA) && defined(SGX_FEATURE_MP_CORE_COUNT_3D) */ -#else -#define SGX_FEATURE_MP_CORE_COUNT (1) -#define SGX_FEATURE_MP_CORE_COUNT_TA (1) -#define SGX_FEATURE_MP_CORE_COUNT_3D (1) -#endif /* SGX_FEATURE_MP */ - -#if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && !defined(SUPPORT_SGX_PRIORITY_SCHEDULING) -#define SUPPORT_SGX_PRIORITY_SCHEDULING -#endif - -#include "img_types.h" - -/****************************************************************************** - End of file (sgxfeaturedefs.h) -******************************************************************************/ diff --git a/pvr-source/services4/srvkm/hwdefs/sgxmmu.h b/pvr-source/services4/srvkm/hwdefs/sgxmmu.h deleted file mode 100755 index a6a907a..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgxmmu.h +++ /dev/null @@ -1,99 +0,0 @@ -/*************************************************************************/ /*! -@Title SGX MMU defines -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@Description Provides SGX MMU declarations and macros -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#if !defined(__SGXMMU_KM_H__) -#define __SGXMMU_KM_H__ - -/* to be implemented */ - -/* SGX MMU maps 4Kb pages */ -#define SGX_MMU_PAGE_SHIFT (12) -#define SGX_MMU_PAGE_SIZE (1U<<SGX_MMU_PAGE_SHIFT) -#define SGX_MMU_PAGE_MASK (SGX_MMU_PAGE_SIZE - 1U) - -/* PD details */ -#define SGX_MMU_PD_SHIFT (10) -#define SGX_MMU_PD_SIZE (1U<<SGX_MMU_PD_SHIFT) -#define SGX_MMU_PD_MASK (0xFFC00000U) - -/* PD Entry details */ -#if defined(SGX_FEATURE_36BIT_MMU) - #define SGX_MMU_PDE_ADDR_MASK (0xFFFFFF00U) - #define SGX_MMU_PDE_ADDR_ALIGNSHIFT (4) -#else - #define SGX_MMU_PDE_ADDR_MASK (0xFFFFF000U) - #define SGX_MMU_PDE_ADDR_ALIGNSHIFT (0) -#endif -#define SGX_MMU_PDE_VALID (0x00000001U) -/* variable page size control field */ -#define SGX_MMU_PDE_PAGE_SIZE_4K (0x00000000U) -#define SGX_MMU_PDE_PAGE_SIZE_16K (0x00000002U) -#define SGX_MMU_PDE_PAGE_SIZE_64K (0x00000004U) -#define SGX_MMU_PDE_PAGE_SIZE_256K (0x00000006U) -#define SGX_MMU_PDE_PAGE_SIZE_1M (0x00000008U) -#define SGX_MMU_PDE_PAGE_SIZE_4M (0x0000000AU) -#define SGX_MMU_PDE_PAGE_SIZE_MASK (0x0000000EU) - -/* PT details */ -#define SGX_MMU_PT_SHIFT (10) -#define SGX_MMU_PT_SIZE (1U<<SGX_MMU_PT_SHIFT) -#define SGX_MMU_PT_MASK (0x003FF000U) - -/* PT Entry details */ -#if defined(SGX_FEATURE_36BIT_MMU) - #define SGX_MMU_PTE_ADDR_MASK (0xFFFFFF00U) - #define SGX_MMU_PTE_ADDR_ALIGNSHIFT (4) -#else - #define SGX_MMU_PTE_ADDR_MASK (0xFFFFF000U) - #define SGX_MMU_PTE_ADDR_ALIGNSHIFT (0) -#endif -#define SGX_MMU_PTE_VALID (0x00000001U) -#define SGX_MMU_PTE_WRITEONLY (0x00000002U) -#define SGX_MMU_PTE_READONLY (0x00000004U) -#define SGX_MMU_PTE_CACHECONSISTENT (0x00000008U) -#define SGX_MMU_PTE_EDMPROTECT (0x00000010U) - -#endif /* __SGXMMU_KM_H__ */ - -/***************************************************************************** - End of file (sgxmmu.h) -*****************************************************************************/ diff --git a/pvr-source/services4/srvkm/hwdefs/sgxmpdefs.h b/pvr-source/services4/srvkm/hwdefs/sgxmpdefs.h deleted file mode 100755 index 4b9649f..0000000 --- a/pvr-source/services4/srvkm/hwdefs/sgxmpdefs.h +++ /dev/null @@ -1,365 +0,0 @@ -/*************************************************************************/ /*! -@Title Hardware defs for SGXMP. -@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved -@License Dual MIT/GPLv2 - -The contents of this file are subject to the MIT license as set out below. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -Alternatively, the contents of this file may be used under the terms of -the GNU General Public License Version 2 ("GPL") in which case the provisions -of GPL are applicable instead of those above. - -If you wish to allow use of your version of this file only under the terms of -GPL, and not to allow others to use your version of this file under the terms -of the MIT license, indicate your decision by deleting the provisions above -and replace them with the notice and other provisions required by GPL as set -out in the file called "GPL-COPYING" included in this distribution. If you do -not delete the provisions above, a recipient may use your version of this file -under the terms of either the MIT license or GPL. - -This License is also included in this distribution in the file called -"MIT-COPYING". - -EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS -PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING -BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR -COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ /**************************************************************************/ - -#ifndef _SGXMPDEFS_KM_H_ -#define _SGXMPDEFS_KM_H_ - -/* Register EUR_CR_MASTER_BIF_CTRL */ -#define EUR_CR_MASTER_BIF_CTRL 0x4C00 -#define EUR_CR_MASTER_BIF_CTRL_NOREORDER_MASK 0x00000001U -#define EUR_CR_MASTER_BIF_CTRL_NOREORDER_SHIFT 0 -#define EUR_CR_MASTER_BIF_CTRL_NOREORDER_SIGNED 0 -#define EUR_CR_MASTER_BIF_CTRL_PAUSE_MASK 0x00000002U -#define EUR_CR_MASTER_BIF_CTRL_PAUSE_SHIFT 1 -#define EUR_CR_MASTER_BIF_CTRL_PAUSE_SIGNED 0 -#define EUR_CR_MASTER_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U -#define EUR_CR_MASTER_BIF_CTRL_CLEAR_FAULT_SHIFT 4 -#define EUR_CR_MASTER_BIF_CTRL_CLEAR_FAULT_SIGNED 0 -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_PTLA_MASK 0x00010000U -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_PTLA_SHIFT 16 -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_PTLA_SIGNED 0 -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_VDM_MASK 0x00020000U -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SHIFT 17 -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SIGNED 0 -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_IPF_MASK 0x00040000U -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SHIFT 18 -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SIGNED 0 -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19 -#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0 -/* Register EUR_CR_MASTER_BIF_CTRL_INVAL */ -#define EUR_CR_MASTER_BIF_CTRL_INVAL 0x4C34 -#define EUR_CR_MASTER_BIF_CTRL_INVAL_PTE_MASK 0x00000004U -#define EUR_CR_MASTER_BIF_CTRL_INVAL_PTE_SHIFT 2 -#define EUR_CR_MASTER_BIF_CTRL_INVAL_PTE_SIGNED 0 -#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_MASK 0x00000008U -#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_SHIFT 3 -#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_SIGNED 0 -/* Register EUR_CR_MASTER_BIF_MMU_CTRL */ -#define EUR_CR_MASTER_BIF_MMU_CTRL 0x4CD0 -#define EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U -#define EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0 -#define EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0 -#define EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U -#define EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1 -#define EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0 -#define EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U -#define EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4 -#define EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0 -/* Register EUR_CR_MASTER_SLC_CTRL */ -#define EUR_CR_MASTER_SLC_CTRL 0x4D00 -#define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK 0x00800000U -#define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_SHIFT 23 -#define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_DISABLE_BURST_EXP_MASK 0x00400000U -#define EUR_CR_MASTER_SLC_CTRL_DISABLE_BURST_EXP_SHIFT 22 -#define EUR_CR_MASTER_SLC_CTRL_DISABLE_BURST_EXP_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ3_MASK 0x00200000U -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ3_SHIFT 21 -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ3_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ2_MASK 0x00100000U -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ2_SHIFT 20 -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ2_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ1_MASK 0x00080000U -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ1_SHIFT 19 -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ1_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_MASK 0x00040000U -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_SHIFT 18 -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_DM_REF_SET_ALL_MASK 0x00010000U -#define EUR_CR_MASTER_SLC_CTRL_DM_REF_SET_ALL_SHIFT 16 -#define EUR_CR_MASTER_SLC_CTRL_DM_REF_SET_ALL_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_MASK 0x0000F000U -#define EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT 12 -#define EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_MASK 0x00000E00U -#define EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT 9 -#define EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_PAUSE_MASK 0x00000100U -#define EUR_CR_MASTER_SLC_CTRL_PAUSE_SHIFT 8 -#define EUR_CR_MASTER_SLC_CTRL_PAUSE_SIGNED 0 -/* Register EUR_CR_MASTER_SLC_CTRL_BYPASS */ -#define EUR_CR_MASTER_SLC_CTRL_BYPASS 0x4D04 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_N_MASK 0x08000000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_N_SHIFT 27 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_N_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK 0x04000000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_SHIFT 26 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE4_MASK 0x02000000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE4_SHIFT 25 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE4_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE3_MASK 0x01000000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE3_SHIFT 24 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE3_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE2_MASK 0x00800000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE2_SHIFT 23 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE2_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE1_MASK 0x00400000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE1_SHIFT 22 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE1_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE0_MASK 0x00200000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE0_SHIFT 21 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE0_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PTLA_MASK 0x00100000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PTLA_SHIFT 20 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PTLA_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ISP2_RCIF_MASK 0x00080000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ISP2_RCIF_SHIFT 19 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ISP2_RCIF_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ZLS_MASK 0x00040000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ZLS_SHIFT 18 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ZLS_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PBE_MASK 0x00020000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PBE_SHIFT 17 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PBE_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_VDM_MASK 0x00010000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_VDM_SHIFT 16 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_VDM_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_MASK 0x00008000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_SHIFT 15 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PDS_MASK 0x00004000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PDS_SHIFT 14 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PDS_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USEC_MASK 0x00002000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USEC_SHIFT 13 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USEC_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_MASK 0x00001000U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_SHIFT 12 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_MASK 0x00000800U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_SHIFT 11 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_MASK 0x00000400U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_SHIFT 10 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_MASK 0x00000200U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_SHIFT 9 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_OBJ_MASK 0x00000100U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_OBJ_SHIFT 8 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_OBJ_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TPF_MASK 0x00000080U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TPF_SHIFT 7 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TPF_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_MASK 0x00000040U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_SHIFT 6 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_CACHE_MASK 0x00000020U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_CACHE_SHIFT 5 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_CACHE_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_MMU_MASK 0x00000010U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_MMU_SHIFT 4 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_MMU_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_EVENT_MASK 0x00000008U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_EVENT_SHIFT 3 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_EVENT_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_PIXEL_MASK 0x00000004U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_PIXEL_SHIFT 2 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_PIXEL_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_VERTEX_MASK 0x00000002U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_VERTEX_SHIFT 1 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_VERTEX_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_ALL_MASK 0x00000001U -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_ALL_SHIFT 0 -#define EUR_CR_MASTER_SLC_CTRL_BYPASS_ALL_SIGNED 0 -/* Register EUR_CR_MASTER_SLC_CTRL_USSE_INVAL */ -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL 0x4D08 -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_ADDR_MASK 0xFFFFFFFFU -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_ADDR_SHIFT 0 -#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_ADDR_SIGNED 0 -/* Register EUR_CR_MASTER_SLC_CTRL_INVAL */ -#define EUR_CR_MASTER_SLC_CTRL_INVAL 0x4D28 -#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_EVENT_MASK 0x00000008U -#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_EVENT_SHIFT 3 -#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_EVENT_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_PIXEL_MASK 0x00000004U -#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_PIXEL_SHIFT 2 -#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_PIXEL_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_VERTEX_MASK 0x00000002U -#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_VERTEX_SHIFT 1 -#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_VERTEX_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_INVAL_ALL_MASK 0x00000001U -#define EUR_CR_MASTER_SLC_CTRL_INVAL_ALL_SHIFT 0 -#define EUR_CR_MASTER_SLC_CTRL_INVAL_ALL_SIGNED 0 -/* Register EUR_CR_MASTER_SLC_CTRL_FLUSH */ -#define EUR_CR_MASTER_SLC_CTRL_FLUSH 0x4D2C -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_EVENT_MASK 0x00000080U -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_EVENT_SHIFT 7 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_EVENT_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_PIXEL_MASK 0x00000040U -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_PIXEL_SHIFT 6 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_PIXEL_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_VERTEX_MASK 0x00000020U -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_VERTEX_SHIFT 5 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_VERTEX_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_MASK 0x00000010U -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_SHIFT 4 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_SIGNED 0 -/* Register EUR_CR_MASTER_SLC_CTRL_FLUSH_INV */ -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV 0x4D34 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_EVENT_MASK 0x00000080U -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_EVENT_SHIFT 7 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_EVENT_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_PIXEL_MASK 0x00000040U -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_PIXEL_SHIFT 6 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_PIXEL_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_VERTEX_MASK 0x00000020U -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_VERTEX_SHIFT 5 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_VERTEX_SIGNED 0 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_ALL_MASK 0x00000010U -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_ALL_SHIFT 4 -#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_ALL_SIGNED 0 -/* Register EUR_CR_MASTER_BREAKPOINT_READ */ -#define EUR_CR_MASTER_BREAKPOINT_READ 0x4F18 -#define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_SHIFT 4 -#define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_SIGNED 0 -/* Register EUR_CR_MASTER_BREAKPOINT_TRAP */ -#define EUR_CR_MASTER_BREAKPOINT_TRAP 0x4F1C -#define EUR_CR_MASTER_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U -#define EUR_CR_MASTER_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U -#define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 -/* Register EUR_CR_MASTER_BREAKPOINT */ -#define EUR_CR_MASTER_BREAKPOINT 0x4F20 -#define EUR_CR_MASTER_BREAKPOINT_ID_MASK 0x00000030U -#define EUR_CR_MASTER_BREAKPOINT_ID_SHIFT 4 -#define EUR_CR_MASTER_BREAKPOINT_ID_SIGNED 0 -#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_MASK 0x00000008U -#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_SHIFT 3 -#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_SIGNED 0 -#define EUR_CR_MASTER_BREAKPOINT_TRAPPED_MASK 0x00000004U -#define EUR_CR_MASTER_BREAKPOINT_TRAPPED_SHIFT 2 -#define EUR_CR_MASTER_BREAKPOINT_TRAPPED_SIGNED 0 -/* Register EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0 */ -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0 0x4F24 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 -/* Register EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1 */ -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1 0x4F28 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 -#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 -/* Register EUR_CR_MASTER_CORE */ -#define EUR_CR_MASTER_CORE 0x4000 -#define EUR_CR_MASTER_CORE_ENABLE_MASK 0x00000003U -#define EUR_CR_MASTER_CORE_ENABLE_SHIFT 0 -#define EUR_CR_MASTER_CORE_ENABLE_SIGNED 0 -/* Register EUR_CR_MASTER_CORE_ID */ -#define EUR_CR_MASTER_CORE_ID 0x4010 -#define EUR_CR_MASTER_CORE_ID_CONFIG_MULTI_MASK 0x00000001U -#define EUR_CR_MASTER_CORE_ID_CONFIG_MULTI_SHIFT 0 -#define EUR_CR_MASTER_CORE_ID_CONFIG_MULTI_SIGNED 0 -#define EUR_CR_MASTER_CORE_ID_CONFIG_BASE_MASK 0x00000002U -#define EUR_CR_MASTER_CORE_ID_CONFIG_BASE_SHIFT 1 -#define EUR_CR_MASTER_CORE_ID_CONFIG_BASE_SIGNED 0 -#define EUR_CR_MASTER_CORE_ID_CONFIG_MASK 0x000000FCU -#define EUR_CR_MASTER_CORE_ID_CONFIG_SHIFT 2 -#define EUR_CR_MASTER_CORE_ID_CONFIG_SIGNED 0 -#define EUR_CR_MASTER_CORE_ID_CONFIG_CORES_MASK 0x00000F00U -#define EUR_CR_MASTER_CORE_ID_CONFIG_CORES_SHIFT 8 -#define EUR_CR_MASTER_CORE_ID_CONFIG_CORES_SIGNED 0 -#define EUR_CR_MASTER_CORE_ID_CONFIG_SLC_MASK 0x0000F000U -#define EUR_CR_MASTER_CORE_ID_CONFIG_SLC_SHIFT 12 -#define EUR_CR_MASTER_CORE_ID_CONFIG_SLC_SIGNED 0 -#define EUR_CR_MASTER_CORE_ID_ID_MASK 0xFFFF0000U -#define EUR_CR_MASTER_CORE_ID_ID_SHIFT 16 -#define EUR_CR_MASTER_CORE_ID_ID_SIGNED 0 -/* Register EUR_CR_MASTER_CORE_REVISION */ -#define EUR_CR_MASTER_CORE_REVISION 0x4014 -#define EUR_CR_MASTER_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU -#define EUR_CR_MASTER_CORE_REVISION_MAINTENANCE_SHIFT 0 -#define EUR_CR_MASTER_CORE_REVISION_MAINTENANCE_SIGNED 0 -#define EUR_CR_MASTER_CORE_REVISION_MINOR_MASK 0x0000FF00U -#define EUR_CR_MASTER_CORE_REVISION_MINOR_SHIFT 8 -#define EUR_CR_MASTER_CORE_REVISION_MINOR_SIGNED 0 -#define EUR_CR_MASTER_CORE_REVISION_MAJOR_MASK 0x00FF0000U -#define EUR_CR_MASTER_CORE_REVISION_MAJOR_SHIFT 16 -#define EUR_CR_MASTER_CORE_REVISION_MAJOR_SIGNED 0 -#define EUR_CR_MASTER_CORE_REVISION_DESIGNER_MASK 0xFF000000U -#define EUR_CR_MASTER_CORE_REVISION_DESIGNER_SHIFT 24 -#define EUR_CR_MASTER_CORE_REVISION_DESIGNER_SIGNED 0 -/* Register EUR_CR_MASTER_SOFT_RESET */ -#define EUR_CR_MASTER_SOFT_RESET 0x4080 -#define EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(i) (0x00000001U << (0 + ((i) * 1))) -#define EUR_CR_MASTER_SOFT_RESET_CORE_RESET_SHIFT(i) (0 + ((i) * 1)) -#define EUR_CR_MASTER_SOFT_RESET_CORE_RESET_REGNUM(i) 0x4080 -#define EUR_CR_MASTER_SOFT_RESET_IPF_RESET_MASK 0x00000010U -#define EUR_CR_MASTER_SOFT_RESET_IPF_RESET_SHIFT 4 -#define EUR_CR_MASTER_SOFT_RESET_IPF_RESET_SIGNED 0 -#define EUR_CR_MASTER_SOFT_RESET_DPM_RESET_MASK 0x00000020U -#define EUR_CR_MASTER_SOFT_RESET_DPM_RESET_SHIFT 5 -#define EUR_CR_MASTER_SOFT_RESET_DPM_RESET_SIGNED 0 -#define EUR_CR_MASTER_SOFT_RESET_VDM_RESET_MASK 0x00000040U -#define EUR_CR_MASTER_SOFT_RESET_VDM_RESET_SHIFT 6 -#define EUR_CR_MASTER_SOFT_RESET_VDM_RESET_SIGNED 0 -#define EUR_CR_MASTER_SOFT_RESET_SLC_RESET_MASK 0x00000080U -#define EUR_CR_MASTER_SOFT_RESET_SLC_RESET_SHIFT 7 -#define EUR_CR_MASTER_SOFT_RESET_SLC_RESET_SIGNED 0 -#define EUR_CR_MASTER_SOFT_RESET_BIF_RESET_MASK 0x00000100U -#define EUR_CR_MASTER_SOFT_RESET_BIF_RESET_SHIFT 8 -#define EUR_CR_MASTER_SOFT_RESET_BIF_RESET_SIGNED 0 -#define EUR_CR_MASTER_SOFT_RESET_MCI_RESET_MASK 0x00000200U -#define EUR_CR_MASTER_SOFT_RESET_MCI_RESET_SHIFT 9 -#define EUR_CR_MASTER_SOFT_RESET_MCI_RESET_SIGNED 0 -#define EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_MASK 0x00000400U -#define EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_SHIFT 10 -#define EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_SIGNED 0 - -#endif /* _SGXMPDEFS_KM_H_ */ - |