| Commit message (Collapse) | Author | Age | Files | Lines |
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Refactor code to support multiple mirrored outputs following code.
Change-Id: I60781d707ae68db2dbd2c4c4122b9183633a74be
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0x100 and 0x120 chipsets were added in gralloc_drm_nouveau.c
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Based on the work by pstglia.
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Based on some work by pstglia, one needs to switch off (partially or
fully?) the tiling when creating the BO.
Comment/uncomment the SW_INDICATOR_FULLY_DISABLES_TILING define to
toggle between the two.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
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Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
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- Move MAX macro to gralloc_drm.h
- Drop the freedreno's duplicated ALIGN macro.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
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Change-Id: I029aafe5a99393a4c0f7ff87f422317621fada12
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
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Change-Id: Ifdf23b59542152c364d3ed010a4cc82bbf1a0103
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
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to change in Jelly Bean.
Signed-off-by: Charles Johnson <charles.f.johnson@intel.com>
modified: gralloc.c
modified: gralloc_drm.c
modified: gralloc_drm_intel.c
modified: gralloc_drm_kms.c
modified: gralloc_drm_nouveau.c
modified: gralloc_drm_pipe.c
modified: gralloc_drm_radeon.c
Change-Id: Idd9e533eab366d9f9dc199d961891255a66384a2
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Introduced by the last commit.
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The mode string is "<xres>x<yres>[@<bpp>]".
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