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author | Nick Pelly <npelly@google.com> | 2011-07-14 08:46:46 -0700 |
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committer | Android (Google) Code Review <android-gerrit@google.com> | 2011-07-14 08:46:46 -0700 |
commit | 709ed1de20e4d3d6ab27bee1b2ab3d2c54f43900 (patch) | |
tree | cf01a30e0624a382262881719912f18130547df7 | |
parent | 23a22e9a09b67902c1183c95e6d93e418437c71b (diff) | |
parent | f15b4573a92e737e4aeef195792c6f30cac0f846 (diff) | |
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Merge "Delay 5ms after FW SW reset command due to clock instability."
-rwxr-xr-x[-rw-r--r--] | src/phDnldNfc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/phDnldNfc.c b/src/phDnldNfc.c index 54d5b87..96f48dd 100644..100755 --- a/src/phDnldNfc.c +++ b/src/phDnldNfc.c @@ -39,6 +39,7 @@ ################################################################################ */ #include <stdlib.h> +#include <unistd.h> #include <phNfcConfig.h> #include <phNfcCompId.h> #include <phNfcIoctlCode.h> @@ -2213,6 +2214,11 @@ phDnldNfc_Send_Complete ( { psDnldContext->resp_length = 0; psDnldContext->dnld_retry = 0; + /* clock unstable after SW reset command, especially on UART + * platform because of its sensitivity to clock. Experimentally + * we found clock unstable for 750us. Delay for 5ms to be sure. + */ + usleep(5000); status = phDnldNfc_Set_Seq(psDnldContext, DNLD_SEQ_UPDATE); } |