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| author | Evan Cheng <evan.cheng@apple.com> | 2013-06-04 22:52:09 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2013-06-04 22:52:09 +0000 |
| commit | 00ed010d9ef388d718ac358132848661b286f7b0 (patch) | |
| tree | 5b11f275055bb8987666024a7f0d6aa070c2b2d2 | |
| parent | 8a227084a5b07fa289c34f2b36e12f75b47473d6 (diff) | |
| download | external_llvm-00ed010d9ef388d718ac358132848661b286f7b0.zip external_llvm-00ed010d9ef388d718ac358132848661b286f7b0.tar.gz external_llvm-00ed010d9ef388d718ac358132848661b286f7b0.tar.bz2 | |
Cortex-R5 can issue Thumb2 integer division instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARM.td | 3 | ||||
| -rw-r--r-- | test/CodeGen/ARM/div.ll | 23 | ||||
| -rw-r--r-- | test/CodeGen/Thumb2/div.ll | 20 |
3 files changed, 25 insertions, 21 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 6b8dbb2..6e9d62f 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -177,7 +177,8 @@ def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", FeatureTrustZone]>; def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", "Cortex-R5 ARM processors", - [FeatureSlowFPBrcc, FeatureHWDivARM, + [FeatureSlowFPBrcc, + FeatureHWDiv, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR, FeatureT2XtPk]>; diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll index 82cfca1..a339c81 100644 --- a/test/CodeGen/ARM/div.ll +++ b/test/CodeGen/ARM/div.ll @@ -1,13 +1,14 @@ ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-ARM -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-SWIFT +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV define i32 @f1(i32 %a, i32 %b) { entry: ; CHECK-ARM: f1 ; CHECK-ARM: __divsi3 -; CHECK-SWIFT: f1 -; CHECK-SWIFT: sdiv +; CHECK-HWDIV: f1 +; CHECK-HWDIV: sdiv %tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } @@ -17,8 +18,8 @@ entry: ; CHECK-ARM: f2 ; CHECK-ARM: __udivsi3 -; CHECK-SWIFT: f2 -; CHECK-SWIFT: udiv +; CHECK-HWDIV: f2 +; CHECK-HWDIV: udiv %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } @@ -28,9 +29,9 @@ entry: ; CHECK-ARM: f3 ; CHECK-ARM: __modsi3 -; CHECK-SWIFT: f3 -; CHECK-SWIFT: sdiv -; CHECK-SWIFT: mls +; CHECK-HWDIV: f3 +; CHECK-HWDIV: sdiv +; CHECK-HWDIV: mls %tmp1 = srem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } @@ -40,9 +41,9 @@ entry: ; CHECK-ARM: f4 ; CHECK-ARM: __umodsi3 -; CHECK-SWIFT: f4 -; CHECK-SWIFT: udiv -; CHECK-SWIFT: mls +; CHECK-HWDIV: f4 +; CHECK-HWDIV: udiv +; CHECK-HWDIV: mls %tmp1 = urem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } diff --git a/test/CodeGen/Thumb2/div.ll b/test/CodeGen/Thumb2/div.ll index f89746a..003d717 100644 --- a/test/CodeGen/Thumb2/div.ll +++ b/test/CodeGen/Thumb2/div.ll @@ -3,7 +3,9 @@ ; RUN: llc < %s -march=thumb -mcpu=cortex-m3 -mattr=+thumb2 \ ; RUN: | FileCheck %s -check-prefix=CHECK-THUMBV7M ; RUN: llc < %s -march=thumb -mcpu=swift \ -; RUN: | FileCheck %s -check-prefix=CHECK-SWIFT-T2 +; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV +; RUN: llc < %s -march=thumb -mcpu=cortex-r5 \ +; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV define i32 @f1(i32 %a, i32 %b) { entry: @@ -11,8 +13,8 @@ entry: ; CHECK-THUMB: __divsi3 ; CHECK-THUMBV7M: f1 ; CHECK-THUMBV7M: sdiv -; CHECK-SWIFT-T2: f1 -; CHECK-SWIFT-T2: sdiv +; CHECK-HWDIV: f1 +; CHECK-HWDIV: sdiv %tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } @@ -23,8 +25,8 @@ entry: ; CHECK-THUMB: __udivsi3 ; CHECK-THUMBV7M: f2 ; CHECK-THUMBV7M: udiv -; CHECK-SWIFT-T2: f2 -; CHECK-SWIFT-T2: udiv +; CHECK-HWDIV: f2 +; CHECK-HWDIV: udiv %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } @@ -35,8 +37,8 @@ entry: ; CHECK-THUMB: __modsi3 ; CHECK-THUMBV7M: f3 ; CHECK-THUMBV7M: sdiv -; CHECK-SWIFT-T2: f3 -; CHECK-SWIFT-T2: sdiv +; CHECK-HWDIV: f3 +; CHECK-HWDIV: sdiv %tmp1 = srem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } @@ -47,8 +49,8 @@ entry: ; CHECK-THUMB: __umodsi3 ; CHECK-THUMBV7M: f4 ; CHECK-THUMBV7M: udiv -; CHECK-SWIFT-T2: f4 -; CHECK-SWIFT-T2: udiv +; CHECK-HWDIV: f4 +; CHECK-HWDIV: udiv %tmp1 = urem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } |