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author | Jim Grosbach <grosbach@apple.com> | 2010-11-17 21:57:51 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2010-11-17 21:57:51 +0000 |
commit | 0129be281eea2c22a925873f2e1cd5cc978ae87c (patch) | |
tree | 1a07e428e0bd454cebfd13dabc3620ad19f833bc | |
parent | 8abe08d7f96dc8e6d16e7c20ea35b238c5e39a97 (diff) | |
download | external_llvm-0129be281eea2c22a925873f2e1cd5cc978ae87c.zip external_llvm-0129be281eea2c22a925873f2e1cd5cc978ae87c.tar.gz external_llvm-0129be281eea2c22a925873f2e1cd5cc978ae87c.tar.bz2 |
Fix comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119573 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index ed3ebb7..01ca22c 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -677,7 +677,7 @@ void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Emit the 'add' instruction. - unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100 + unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; |