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| author | Bob Wilson <bob.wilson@apple.com> | 2010-10-15 18:25:59 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-10-15 18:25:59 +0000 |
| commit | 01b35c25deee3d4cab339e620c12c721e627d609 (patch) | |
| tree | 9b643413cd9db1b31498551a6ffba05573280532 | |
| parent | de89b010b0b347cdbd1bc9553a970880a3e721bf (diff) | |
| download | external_llvm-01b35c25deee3d4cab339e620c12c721e627d609.zip external_llvm-01b35c25deee3d4cab339e620c12c721e627d609.tar.gz external_llvm-01b35c25deee3d4cab339e620c12c721e627d609.tar.bz2 | |
Use simple RegState::Define flag instead of getDefRegState(true).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116601 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 836f69d..e16c07d 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -586,7 +586,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { .addReg(0) .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1))) - .addReg(ARM::CPSR, getDefRegState(true)); + .addReg(ARM::CPSR, RegState::Define); MI.eraseFromParent(); break; } @@ -616,7 +616,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) - .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)) + .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) .addReg(DstReg) .addOperand(MI.getOperand(2)); TransferImpOps(MI, MIB1, MIB2); @@ -640,7 +640,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode == ARM::MOVi32imm ? ARM::MOVTi16 : ARM::t2MOVTi16)) - .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)) + .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) .addReg(DstReg); if (MO.isImm()) { @@ -677,13 +677,13 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VMOVQ)) .addReg(EvenDst, - getDefRegState(true) | getDeadRegState(DstIsDead)) + RegState::Define | getDeadRegState(DstIsDead)) .addReg(EvenSrc, getKillRegState(SrcIsKill))); MachineInstrBuilder Odd = AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VMOVQ)) .addReg(OddDst, - getDefRegState(true) | getDeadRegState(DstIsDead)) + RegState::Define | getDeadRegState(DstIsDead)) .addReg(OddSrc, getKillRegState(SrcIsKill))); TransferImpOps(MI, Even, Odd); MI.eraseFromParent(); |