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| author | Jim Grosbach <grosbach@apple.com> | 2011-12-20 00:59:38 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-12-20 00:59:38 +0000 |
| commit | 04b5d93250bef585631a583a85f6733b1bdc8c52 (patch) | |
| tree | 946b0eac66d3cf78fa40f2a13c56b139cf5c5d62 | |
| parent | ea93373a0a1bf1d087f5414e566384c2af3ebf09 (diff) | |
| download | external_llvm-04b5d93250bef585631a583a85f6733b1bdc8c52.zip external_llvm-04b5d93250bef585631a583a85f6733b1bdc8c52.tar.gz external_llvm-04b5d93250bef585631a583a85f6733b1bdc8c52.tar.bz2 | |
ARM assembly shifts by zero should be plain 'mov' instructions.
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 17 | ||||
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 17 |
2 files changed, 34 insertions, 0 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 9852cc8..ac7532b 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5945,6 +5945,23 @@ processInstruction(MCInst &Inst, } break; } + case ARM::MOVsi: { + ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); + if (SOpc == ARM_AM::rrx) return false; + if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { + // Shifting by zero is accepted as a vanilla 'MOVr' + MCInst TmpInst; + TmpInst.setOpcode(ARM::MOVr); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(Inst.getOperand(3)); + TmpInst.addOperand(Inst.getOperand(4)); + TmpInst.addOperand(Inst.getOperand(5)); + Inst = TmpInst; + return true; + } + return false; + } case ARM::t2IT: { // The mask bits for all but the first condition are represented as // the low bit of the condition code value implies 't'. We currently diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 080bc6f..a51b00b 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -904,11 +904,28 @@ Lforward: movs r2, r3 moveq r2, r3 movseq r2, r3 + mov r12, r8, lsl #(2 - 2) + lsl r2, r3, #(2 - 2) + mov r12, r8, lsr #(2 - 2) + lsr r2, r3, #(2 - 2) + mov r12, r8, asr #(2 - 2) + asr r2, r3, #(2 - 2) + mov r12, r8, ror #(2 - 2) + ror r2, r3, #(2 - 2) @ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] @ CHECK: movs r2, r3 @ encoding: [0x03,0x20,0xb0,0xe1] @ CHECK: moveq r2, r3 @ encoding: [0x03,0x20,0xa0,0x01] @ CHECK: movseq r2, r3 @ encoding: [0x03,0x20,0xb0,0x01] +@ CHECK: mov r12, r8 @ encoding: [0x08,0xc0,0xa0,0xe1] +@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] +@ CHECK: mov r12, r8 @ encoding: [0x08,0xc0,0xa0,0xe1] +@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] +@ CHECK: mov r12, r8 @ encoding: [0x08,0xc0,0xa0,0xe1] +@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] +@ CHECK: mov r12, r8 @ encoding: [0x08,0xc0,0xa0,0xe1] +@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] + @------------------------------------------------------------------------------ @ MOVT |