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authorAnton Korobeynikov <asl@math.spbu.ru>2009-08-05 20:15:19 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2009-08-05 20:15:19 +0000
commit058c251d4ac23bb3f9ca66eb0e465fa2c6c66f42 (patch)
treecf288f41bb91e1f577ba9869b478e0de3f6d9a59
parentbe0cf7dbc2d230e10f6eec92fb2219ce69a925cc (diff)
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Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
hardfloat case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78237 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp18
1 files changed, 7 insertions, 11 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 252d920..155ef59 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -1461,21 +1461,17 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
} else {
TargetRegisterClass *RC;
- if (FloatABIType == FloatABI::Hard && RegVT == MVT::f32)
+ if (RegVT == MVT::f32)
RC = ARM::SPRRegisterClass;
- else if (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)
+ else if (RegVT == MVT::f64)
RC = ARM::DPRRegisterClass;
- else if (FloatABIType == FloatABI::Hard && RegVT == MVT::v2f64)
+ else if (RegVT == MVT::v2f64)
RC = ARM::QPRRegisterClass;
- else if (AFI->isThumb1OnlyFunction())
- RC = ARM::tGPRRegisterClass;
+ else if (RegVT == MVT::i32)
+ RC = (AFI->isThumb1OnlyFunction() ?
+ ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
else
- RC = ARM::GPRRegisterClass;
-
- assert((RegVT == MVT::i32 || RegVT == MVT::f32 ||
- (FloatABIType == FloatABI::Hard &&
- ((RegVT == MVT::f64) || (RegVT == MVT::v2f64)))) &&
- "RegVT not supported by FORMAL_ARGUMENTS Lowering");
+ llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
// Transform the arguments in physical registers into virtual ones.
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);