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| author | Owen Anderson <resistor@mac.com> | 2011-07-27 20:29:48 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-07-27 20:29:48 +0000 |
| commit | 06470311c574da4f83f91400234a1e1fc4c9ea1b (patch) | |
| tree | 684fd4d18de2a41f529b2c4a8d00ef40105b9283 | |
| parent | 772fe17a6d07304ae2e6b3052bbb24ebb751f0f3 (diff) | |
| download | external_llvm-06470311c574da4f83f91400234a1e1fc4c9ea1b.zip external_llvm-06470311c574da4f83f91400234a1e1fc4c9ea1b.tar.gz external_llvm-06470311c574da4f83f91400234a1e1fc4c9ea1b.tar.bz2 | |
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 32 | ||||
| -rw-r--r-- | test/MC/ARM/arm_addrmode2.s | 1 |
2 files changed, 31 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 1061fbd..4c6bace 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2090,22 +2090,50 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb), // STRT, STRBT, and STRHT are for disassembly only. -def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr), +def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, ldst_so_reg:$addr), IndexModePost, StFrm, IIC_iStore_ru, "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 1; + let Inst{21} = 1; // overwrite + let Inst{4} = 0; + let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; +} + +def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addrmode_imm12:$addr), + IndexModePost, StFrm, IIC_iStore_ru, + "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", + [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 0; + let Inst{21} = 1; // overwrite + let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; +} + + +def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, ldst_so_reg:$addr), + IndexModePost, StFrm, IIC_iStore_bh_ru, + "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb", + [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 1; let Inst{21} = 1; // overwrite + let Inst{4} = 0; let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; } -def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr), +def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePost, StFrm, IIC_iStore_bh_ru, "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb", [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 0; let Inst{21} = 1; // overwrite let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; } + def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, IIC_iStore_bh_ru, "strht", "\t$Rt, $addr", "$addr.base = $base_wb", diff --git a/test/MC/ARM/arm_addrmode2.s b/test/MC/ARM/arm_addrmode2.s index ca99233..76fe027 100644 --- a/test/MC/ARM/arm_addrmode2.s +++ b/test/MC/ARM/arm_addrmode2.s @@ -1,4 +1,5 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s +@ XFAIL: * @ Post-indexed @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6] |