diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2011-08-31 02:05:24 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-08-31 02:05:24 +0000 |
| commit | 0899f5c62dc63d199185a2d09e434d992975e700 (patch) | |
| tree | 2f96b83bd5f5de106a95aaad769ebb56eccdd98f | |
| parent | 3d93861c23b1bafa8ae609de94edd5740ffbf6b9 (diff) | |
| download | external_llvm-0899f5c62dc63d199185a2d09e434d992975e700.zip external_llvm-0899f5c62dc63d199185a2d09e434d992975e700.tar.gz external_llvm-0899f5c62dc63d199185a2d09e434d992975e700.tar.bz2 | |
Fix (movhps load) lowering / pattern to match more cases. rdar://10050549
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138848 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 7 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 3 | ||||
| -rw-r--r-- | test/CodeGen/X86/vec_shuffle-38.ll | 19 |
3 files changed, 26 insertions, 3 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index effe06e..7fa0dba 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -6236,8 +6236,11 @@ SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, if (HasSSE2 && VT == MVT::v2f64) return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); - // v4f32 or v4i32 - return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG); + // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) + return DAG.getNode(ISD::BITCAST, dl, VT, + getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, + DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), + DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); } static diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index e8a38f5..595010d 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -691,11 +691,12 @@ let Predicates = [HasSSE1] in { // MOVHPS patterns def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>; + def : Pat<(X86Movlhps VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), (MOVHPSrm VR128:$src1, addr:$src2)>; def : Pat<(X86Movlhps VR128:$src1, - (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), + (bc_v4f32 (v2i64 (X86vzload addr:$src2)))), (MOVHPSrm VR128:$src1, addr:$src2)>; // MOVLHPS patterns diff --git a/test/CodeGen/X86/vec_shuffle-38.ll b/test/CodeGen/X86/vec_shuffle-38.ll index fe83cd4..978f59e 100644 --- a/test/CodeGen/X86/vec_shuffle-38.ll +++ b/test/CodeGen/X86/vec_shuffle-38.ll @@ -24,3 +24,22 @@ define <2 x i64> @hdi(<2 x i64> %p) nounwind optsize ssp { ret <2 x i64> %shuffle } +; rdar://10050549 +%struct.Float2 = type { float, float } + +define <4 x float> @loadhpi(%struct.Float2* %vPtr, <4 x float> %vecin1) nounwind readonly ssp { +entry: +; CHECK: loadhpi +; CHECK-NOT: movq +; CHECK: movhps ( + %tmp1 = bitcast %struct.Float2* %vPtr to <1 x i64>* + %addptr7 = getelementptr inbounds <1 x i64>* %tmp1, i64 0 + %tmp2 = bitcast <1 x i64>* %addptr7 to float* + %tmp3 = load float* %tmp2, align 4 + %vec = insertelement <4 x float> undef, float %tmp3, i32 0 + %addptr.i12 = getelementptr inbounds float* %tmp2, i64 1 + %tmp4 = load float* %addptr.i12, align 4 + %vecin2 = insertelement <4 x float> %vec, float %tmp4, i32 1 + %shuffle = shufflevector <4 x float> %vecin1, <4 x float> %vecin2, <4 x i32> <i32 0, i32 1, i32 4, i32 5> + ret <4 x float> %shuffle +} |