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authorChad Rosier <mcrosier@apple.com>2013-02-26 20:22:30 +0000
committerChad Rosier <mcrosier@apple.com>2013-02-26 20:22:30 +0000
commit0908bcbf4483d1245f2156624268cf0922e874c9 (patch)
tree5c6c9fa6125b34d575574126b5e839d4bd1ee383
parentac67b50fcfaab20829b4bce32cfdce77507f6c72 (diff)
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Add a test case for r176066.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176119 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--test/CodeGen/X86/fast-isel-args-fail.ll10
1 files changed, 10 insertions, 0 deletions
diff --git a/test/CodeGen/X86/fast-isel-args-fail.ll b/test/CodeGen/X86/fast-isel-args-fail.ll
new file mode 100644
index 0000000..4995baa
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-args-fail.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-apple-darwin10
+; Requires: Asserts
+
+; Previously, this would cause an assert.
+define i31 @t1(i31 %a, i31 %b, i31 %c) {
+entry:
+ %add = add nsw i31 %b, %a
+ %add1 = add nsw i31 %add, %c
+ ret i31 %add1
+}