Do not use getTargetNode() and SelectNodeTo() which takes more than 3

SDOperand arguments. Use the variants which take an array and number instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29907 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 77 insertions, 66 deletions

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 52aa8bb..da9be76 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -442,10 +442,11 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
        Opc = Alpha::STT;
      } else
        assert(0 && "Unknown operand"); 
-     Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i], 
-                                             getI64Imm((i - 6) * 8), 
-                                             CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
-                                             Chain), 0);
+
+     SDOperand Ops[] = { CallOperands[i],  getI64Imm((i - 6) * 8), 
+                         CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
+                         Chain };
+     Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
    }
    for (int i = 0; i < std::min(6, count); ++i) {
      if (MVT::isInteger(TypeOperands[i])) {
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 3948c53..9365b54 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -204,18 +204,22 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
     }
     
     SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
-    
+
+    SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
     TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
-                                            TmpF4, TmpF5, F1, TmpPR), 0);
+                                            OpsE0, 4), 0);
     Chain = TmpE0.getValue(1);
+    SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
     TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
-                                            TmpF5, TmpE0, TmpF5, TmpPR), 0);
+                                            OpsY1, 4), 0);
     Chain = TmpY1.getValue(1);
+    SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
     TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
-                                            TmpE0, TmpE0, F0, TmpPR), 0);
+                                            OpsE1, 4), 0);
     Chain = TmpE1.getValue(1);
+    SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
     TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
-                                            TmpY1, TmpE1, TmpY1, TmpPR), 0);
+                                            OpsY2, 4), 0);
     Chain = TmpY2.getValue(1);
     
     if(isFP) { // if this is an FP divide, we finish up here and exit early
@@ -223,45 +227,53 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
         assert(0 && "Sorry, try another FORTRAN compiler.");
  
       SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
-      
+
+      SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
       TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
-                                              TmpE1, TmpE1, F0, TmpPR), 0);
+                                              OpsE2, 4), 0);
       Chain = TmpE2.getValue(1);
+      SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
       TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
-                                              TmpY2, TmpE2, TmpY2, TmpPR), 0);
+                                              OpsY3, 4), 0);
       Chain = TmpY3.getValue(1);
+      SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
       TmpQ0 =
         SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
-                                        Tmp1, TmpY3, F0, TmpPR), 0);
+                                        OpsQ0, 4), 0);
       Chain = TmpQ0.getValue(1);
+      SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
       TmpR0 =
         SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
-                                        Tmp2, TmpQ0, Tmp1, TmpPR), 0);
+                                        OpsR0, 4), 0);
       Chain = TmpR0.getValue(1);
 
 // we want Result to have the same target register as the frcpa, so
 // we two-address hack it. See the comment "for this to work..." on
 // page 48 of Intel application note #245415
+      SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
       Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
-                                     TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
+                                     Ops, 5);
       Chain = SDOperand(Result, 1);
       return Result; // XXX: early exit!
     } else { // this is *not* an FP divide, so there's a bit left to do:
     
       SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
-      
+
+      SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
       TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
-                                              TmpF3, TmpY2, F0, TmpPR), 0);
+                                              OpsQ2, 4), 0);
       Chain = TmpQ2.getValue(1);
+      SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
       TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
-                                              TmpF4, TmpQ2, TmpF3, TmpPR), 0);
+                                              OpsR2, 4), 0);
       Chain = TmpR2.getValue(1);
       
 // we want TmpQ3 to have the same target register as the frcpa? maybe we
 // should two-address hack it. See the comment "for this to work..." on page
 // 48 of Intel application note #245415
+      SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
       TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
-                                         TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR), 0);
+                                         OpsQ3, 5), 0);
       Chain = TmpQ3.getValue(1);
 
       // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 507a2a3..8c0b399 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -457,8 +457,9 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
       AddToISelQueue(Tmp3);
       AddToISelQueue(Op1);
       SH &= 31;
-      return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp3, Op1,
-                                   getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
+      SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
+                          getI32Imm(ME) };
+      return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
     }
   }
   return 0;
@@ -809,10 +810,11 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
       AddToISelQueue(Op);
       switch (CC) {
       default: break;
-      case ISD::SETEQ:
+      case ISD::SETEQ: {
         Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
-        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
-                                    getI32Imm(5), getI32Imm(31));
+        SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
+        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
+      }
       case ISD::SETNE: {
         SDOperand AD =
           SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
@@ -820,15 +822,16 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
         return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, 
                                     AD.getValue(1));
       }
-      case ISD::SETLT:
-        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
-                                    getI32Imm(31), getI32Imm(31));
+      case ISD::SETLT: {
+        SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
+      }
       case ISD::SETGT: {
         SDOperand T =
           SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
         T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
-        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
-                                    getI32Imm(31), getI32Imm(31));
+        SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
       }
       }
     } else if (Imm == ~0U) {        // setcc op, -1
@@ -855,16 +858,16 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
                                                        getI32Imm(1)), 0);
         SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
                                                        Op), 0);
-        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
-                                    getI32Imm(31), getI32Imm(31));
+        SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
       }
-      case ISD::SETGT:
-        Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op,
-                                             getI32Imm(1), getI32Imm(31),
-                                             getI32Imm(31)), 0);
+      case ISD::SETGT: {
+        SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+        Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
         return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, 
                                     getI32Imm(1));
       }
+      }
     }
   }
   
@@ -886,15 +889,13 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
   else
     IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
   
+  SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
+                      getI32Imm(31), getI32Imm(31) };
   if (!Inv) {
-    return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
-                                getI32Imm((32-(3-Idx)) & 31),
-                                getI32Imm(31), getI32Imm(31));
+    return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
   } else {
     SDOperand Tmp =
-      SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
-                                      getI32Imm((32-(3-Idx)) & 31),
-                                      getI32Imm(31),getI32Imm(31)), 0);
+      SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
     return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
   }
 }
@@ -990,9 +991,8 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
         isRunOfOnes(Imm, MB, ME);
         SH = 0;
       }
-      return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val,
-                                  getI32Imm(SH), getI32Imm(MB),
-                                  getI32Imm(ME));
+      SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
+      return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
     }
     // ISD::OR doesn't get all the bitfield insertion fun.
     // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
@@ -1004,10 +1004,10 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
       if (isRunOfOnes(Imm, MB, ME)) {
         AddToISelQueue(N->getOperand(0).getOperand(0));
         AddToISelQueue(N->getOperand(0).getOperand(1));
-        return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32,
-                                     N->getOperand(0).getOperand(0),
-                                     N->getOperand(0).getOperand(1),
-                                     getI32Imm(0), getI32Imm(MB),getI32Imm(ME));
+        SDOperand Ops[] = { N->getOperand(0).getOperand(0),
+                            N->getOperand(0).getOperand(1),
+                            getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
+        return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
       }
     }
     
@@ -1026,10 +1026,9 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
     if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
         isRotateAndMask(N, Imm, true, SH, MB, ME)) {
       AddToISelQueue(N->getOperand(0).getOperand(0));
-      return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
-                                  N->getOperand(0).getOperand(0),
-                                  getI32Imm(SH), getI32Imm(MB),
-                                  getI32Imm(ME));
+      SDOperand Ops[] = { N->getOperand(0).getOperand(0),
+                          getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
+      return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
     }
     
     // Other cases are autogenerated.
@@ -1040,10 +1039,9 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
     if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
         isRotateAndMask(N, Imm, true, SH, MB, ME)) { 
       AddToISelQueue(N->getOperand(0).getOperand(0));
-      return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
-                                  N->getOperand(0).getOperand(0),
-                                  getI32Imm(SH), getI32Imm(MB),
-                                  getI32Imm(ME));
+      SDOperand Ops[] = { N->getOperand(0).getOperand(0),
+                          getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
+      return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
     }
     
     // Other cases are autogenerated.
@@ -1087,17 +1085,17 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
 
     AddToISelQueue(N->getOperand(2));
     AddToISelQueue(N->getOperand(3));
-    return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
-                                N->getOperand(2), N->getOperand(3),
-                                getI32Imm(BROpc));
+    SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
+                        getI32Imm(BROpc) };
+    return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
   }
   case ISD::BR_CC: {
     AddToISelQueue(N->getOperand(0));
     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
     SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
-    return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, 
-                                CondCode, getI32Imm(getBCCForSetCC(CC)), 
-                                N->getOperand(4), N->getOperand(0));
+    SDOperand Ops[] = { CondCode, getI32Imm(getBCCForSetCC(CC)), 
+                        N->getOperand(4), N->getOperand(0) };
+    return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, Ops, 4);
   }
   case ISD::BRIND: {
     // FIXME: Should custom lower this.
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 5720011..e534c56 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -723,9 +723,9 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
         AddToISelQueue(Tmp1);
         AddToISelQueue(Tmp2);
         AddToISelQueue(Tmp3);
+        SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
         SDNode *CNode =
-          CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
-                                Tmp2, Tmp3, Chain, InFlag);
+          CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
         Chain  = SDOperand(CNode, 0);
         InFlag = SDOperand(CNode, 1);
       } else {
@@ -827,9 +827,9 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
         AddToISelQueue(Tmp1);
         AddToISelQueue(Tmp2);
         AddToISelQueue(Tmp3);
+        SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
         SDNode *CNode =
-          CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
-                                Tmp2, Tmp3, Chain, InFlag);
+          CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
         Chain  = SDOperand(CNode, 0);
         InFlag = SDOperand(CNode, 1);
       } else {