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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-05-20 15:02:24 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-05-20 15:02:24 +0000 |
| commit | 0bbfc9313c2b6fc63ae19174858bbaab1c774661 (patch) | |
| tree | e761697a128e5c31e191cdbc0b927cd3f963186e | |
| parent | ba534c21437ba133cb9d6b3f9dae80fa9c4f0cb7 (diff) | |
| download | external_llvm-0bbfc9313c2b6fc63ae19174858bbaab1c774661.zip external_llvm-0bbfc9313c2b6fc63ae19174858bbaab1c774661.tar.gz external_llvm-0bbfc9313c2b6fc63ae19174858bbaab1c774661.tar.bz2 | |
R600/SI: Add pattern for rotr
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182286 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 2 | ||||
| -rw-r--r-- | test/CodeGen/R600/rotr.ll | 28 |
2 files changed, 21 insertions, 9 deletions
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index f557922..7c725cc 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -964,6 +964,8 @@ def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>; def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>; //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; +def : ROTRPattern <V_ALIGNBIT_B32>; + def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; diff --git a/test/CodeGen/R600/rotr.ll b/test/CodeGen/R600/rotr.ll index 75232fe..8bb5eae 100644 --- a/test/CodeGen/R600/rotr.ll +++ b/test/CodeGen/R600/rotr.ll @@ -1,8 +1,13 @@ -; RUN: llc < %s -debug-only=isel -march=r600 -mcpu=redwood -o - 2>&1 | FileCheck %s +; RUN: llc < %s -debug-only=isel -march=r600 -mcpu=redwood -o - 2>&1 | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -debug-only=isel -march=r600 -mcpu=SI -o - 2>&1 | FileCheck --check-prefix=SI-CHECK %s -; CHECK: rotr -; CHECK: @rotr -; CHECK: BIT_ALIGN_INT +; R600-CHECK: rotr +; R600-CHECK: @rotr +; R600-CHECK: BIT_ALIGN_INT + +; SI-CHECK: rotr +; SI-CHECK: @rotr +; SI-CHECK: V_ALIGNBIT_B32 define void @rotr(i32 addrspace(1)* %in, i32 %x, i32 %y) { entry: %0 = sub i32 32, %y @@ -13,11 +18,16 @@ entry: ret void } -; CHECK: rotr -; CHECK: @rotl -; CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x -; CHECK-NEXT: 32 -; CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[xyzw]}} +; R600-CHECK: rotr +; R600-CHECK: @rotl +; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x +; R600-CHECK-NEXT: 32 +; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[xyzw]}} + +; SI-CHECK: rotr +; SI-CHECK: @rotl +; SI-CHECK: V_SUB_I32_e32 [[DST:VGPR[0-9]+]], 32, {{VGPR[0-9]+}} +; SI-CHECK: V_ALIGNBIT_B32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}, [[DST]] define void @rotl(i32 addrspace(1)* %in, i32 %x, i32 %y) { entry: %0 = shl i32 %x, %y |