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author | Anton Korobeynikov <asl@math.spbu.ru> | 2008-10-10 20:28:10 +0000 |
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committer | Anton Korobeynikov <asl@math.spbu.ru> | 2008-10-10 20:28:10 +0000 |
commit | 0eefda1335f5e86f95dbb58352321a43237e1089 (patch) | |
tree | f68b095414ffbd3172b833bd5a41c8ea8a86c443 | |
parent | 53835708e1540299eefdbbb70be2ebb1847dd3eb (diff) | |
download | external_llvm-0eefda1335f5e86f95dbb58352321a43237e1089.zip external_llvm-0eefda1335f5e86f95dbb58352321a43237e1089.tar.gz external_llvm-0eefda1335f5e86f95dbb58352321a43237e1089.tar.bz2 |
Add rudimentary support for 'r' register operand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57359 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 52 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcISelLowering.h | 29 |
2 files changed, 70 insertions, 11 deletions
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 25fef42..dc06078 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/ADT/VectorExtras.h" using namespace llvm; @@ -944,3 +945,54 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } + +//===----------------------------------------------------------------------===// +// Sparc Inline Assembly Support +//===----------------------------------------------------------------------===// + +/// getConstraintType - Given a constraint letter, return the type of +/// constraint it is for this target. +SparcTargetLowering::ConstraintType +SparcTargetLowering::getConstraintType(const std::string &Constraint) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + default: break; + case 'r': return C_RegisterClass; + } + } + + return TargetLowering::getConstraintType(Constraint); +} + +std::pair<unsigned, const TargetRegisterClass*> +SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, + MVT VT) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + case 'r': + return std::make_pair(0U, SP::IntRegsRegisterClass); + } + } + + return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); +} + +std::vector<unsigned> SparcTargetLowering:: +getRegClassForInlineAsmConstraint(const std::string &Constraint, + MVT VT) const { + if (Constraint.size() != 1) + return std::vector<unsigned>(); + + switch (Constraint[0]) { + default: break; + case 'r': + return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3, + SP::L4, SP::L5, SP::L6, SP::L7, + SP::I0, SP::I1, SP::I2, SP::I3, + SP::I4, SP::I5, + SP::O0, SP::O1, SP::O2, SP::O3, + SP::O4, SP::O5, SP::O7, 0); + } + + return std::vector<unsigned>(); +} diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index d71f51c..ea3171d 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -28,41 +28,48 @@ namespace llvm { BRFCC, // Branch to dest on fcc condition SELECT_ICC, // Select between two values using the current ICC flags. SELECT_FCC, // Select between two values using the current FCC flags. - + Hi, Lo, // Hi/Lo operations, typically on a global address. - + FTOI, // FP to Int within a FP register. ITOF, // Int to FP within a FP register. - + CALL, // A call instruction. RET_FLAG // Return with a flag operand. }; } - + class SparcTargetLowering : public TargetLowering { int VarArgsFrameOffset; // Frame offset to start of varargs area. public: SparcTargetLowering(TargetMachine &TM); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); - + int getVarArgsFrameOffset() const { return VarArgsFrameOffset; } - - /// computeMaskedBitsForTargetNode - Determine which of the bits specified - /// in Mask are known to be either zero or one and return them in the + + /// computeMaskedBitsForTargetNode - Determine which of the bits specified + /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. virtual void computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, - APInt &KnownZero, + APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth = 0) const; - + virtual void LowerArguments(Function &F, SelectionDAG &DAG, SmallVectorImpl<SDValue> &ArgValues); virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB); - + virtual const char *getTargetNodeName(unsigned Opcode) const; + + ConstraintType getConstraintType(const std::string &Constraint) const; + std::pair<unsigned, const TargetRegisterClass*> + getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; + std::vector<unsigned> + getRegClassForInlineAsmConstraint(const std::string &Constraint, + MVT VT) const; }; } // end namespace llvm |