Initial JIT support for ARM by Raul Fernandes Herbster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8

9 files changed, 889 insertions, 275 deletions

diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index 0272004..6f5719f 100644
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -102,11 +102,13 @@ def ARMInstrInfo : InstrInfo {
   let TSFlagsFields = ["AddrModeBits",
                        "SizeFlag",
                        "IndexModeBits",
-                       "Opcode"];
+                       "Opcode",
+                       "Form"];
   let TSFlagsShifts = [0,
                        4,
                        7,
-                       9];
+                       9,
+                       13];
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index ed1d287..6066671 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -16,6 +16,8 @@
 #include "ARMInstrInfo.h"
 #include "ARMSubtarget.h"
 #include "ARMTargetMachine.h"
+#include "ARMRelocations.h"
+#include "ARMAddressingModes.h"
 #include "ARM.h"
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/MachineCodeEmitter.h"
@@ -52,8 +54,19 @@ namespace {
     }
 
     void emitInstruction(const MachineInstr &MI);
+    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
+    int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
+    unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
+
+    void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
+    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
+    void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
+                              int Disp = 0, unsigned PCAdj = 0 );
+    void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
+                              unsigned PCAdj = 0);
 
   private:
+    int getShiftOp(const MachineOperand &MO);
 
   };
   char Emitter::ID = 0;
@@ -87,6 +100,437 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) {
   return false;
 }
 
+unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
+  return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
+}
+
+int Emitter::getShiftOp(const MachineOperand &MO) {
+  unsigned ShiftOp = 0x0;
+  switch(ARM_AM::getAM2ShiftOpc(MO.getImmedValue())) {
+  default: assert(0 && "Unknown shift opc!");
+  case ARM_AM::asr:
+    ShiftOp = 0X2;
+    break;
+  case ARM_AM::lsl:
+    ShiftOp = 0X0;
+    break;
+  case ARM_AM::lsr:
+    ShiftOp = 0X1;
+    break;
+  case ARM_AM::ror:
+  case ARM_AM::rrx:
+    ShiftOp = 0X3;
+    break;
+  }
+  return ShiftOp;
+}
+
+int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) {
+  intptr_t rv = 0;
+  const MachineOperand &MO = MI.getOperand(OpIndex);
+  if (MO.isRegister()) {
+    assert(MRegisterInfo::isPhysicalRegister(MO.getReg()));
+    rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
+  } else if (MO.isImmediate()) {
+    rv = MO.getImmedValue();
+  } else if (MO.isGlobalAddress() || MO.isExternalSymbol() ||
+             MO.isConstantPoolIndex() || MO.isJumpTableIndex()) {
+
+    if (MO.isGlobalAddress()) {
+      emitGlobalAddressForCall(MO.getGlobal(), true);
+    } else if (MO.isExternalSymbol()) {
+      emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
+    } else if (MO.isConstantPoolIndex()) {
+      emitConstPoolAddress(MO.getConstantPoolIndex(), ARM::reloc_arm_relative);
+    } else if (MO.isJumpTableIndex()) {
+      emitJumpTableAddress(MO.getJumpTableIndex(), ARM::reloc_arm_relative);
+    }
+
+  }
+  return rv;
+}
+
+/// emitGlobalAddressForCall - Emit the specified address to the code stream
+/// assuming this is part of a function call, which is PC relative.
+///
+void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
+  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
+                                      ARM::reloc_arm_branch, GV, 0,
+                                      DoesntNeedStub));
+}
+
+/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
+/// be emitted to the current location in the function, and allow it to be PC
+/// relative.
+void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
+  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
+                                                 Reloc, ES));
+}
+
+/// emitConstPoolAddress - Arrange for the address of an constant pool
+/// to be emitted to the current location in the function, and allow it to be PC
+/// relative.
+void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
+                                   int Disp /* = 0 */,
+                                   unsigned PCAdj /* = 0 */) {
+  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
+                                                    Reloc, CPI, PCAdj));
+}
+
+/// emitJumpTableAddress - Arrange for the address of a jump table to
+/// be emitted to the current location in the function, and allow it to be PC
+/// relative.
+void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
+                                   unsigned PCAdj /* = 0 */) {
+  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
+                                                    Reloc, JTI, PCAdj));
+}
+
+
+
 void Emitter::emitInstruction(const MachineInstr &MI) {
   NumEmitted++;  // Keep track of the # of mi's emitted
+  MCE.emitWordLE(getBinaryCodeForInstr(MI));
+}
+
+unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
+  const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
+  const unsigned opcode = MI.getOpcode();
+  unsigned Value = 0xE0000000;
+  unsigned op;
+
+  switch (Desc->TSFlags & ARMII::AddrModeMask) {
+  case ARMII::AddrModeNone: {
+    switch(Desc->TSFlags & ARMII::FormMask) {
+    default: {
+      assert(0 && "Unknown instruction subtype!");
+      if(opcode == ARM::CLZ) {
+        // set first operand
+        op = getMachineOpValue(MI,0);
+        Value |= op << 12;
+
+        // set second operand
+        op = getMachineOpValue(MI,1);
+        Value |= op;
+      }
+      break;
+    }
+    case ARMII::MulFrm: {
+      Value |= 9 << 4;
+
+      unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
+      Value |= BaseOpcode << 20;
+
+      bool isMUL = opcode == ARM::MUL;
+      bool isMLA = opcode == ARM::MLA;
+
+      // set first operand
+      op = getMachineOpValue(MI,0);
+      Value |= op << (isMUL || isMLA ? 16 : 12);
+
+      // set second operand
+      op = getMachineOpValue(MI,1);
+      Value |= op << (isMUL || isMLA ? 0 : 16);
+
+      // set third operand
+      op = getMachineOpValue(MI,2);
+      Value |= op << (isMUL || isMLA ? 8 : 0);
+
+      if (!isMUL) {
+        op = getMachineOpValue(MI,3);
+        Value |= op << (isMLA ? 12 : 8);
+      }
+
+      break;
+    }
+    case ARMII::Branch: {
+      unsigned BaseOpcode = getBaseOpcodeFor(Desc);
+      Value |= BaseOpcode << 24;
+
+      op = getMachineOpValue(MI,0);
+      Value |= op;
+
+      break;
+    }
+    case ARMII::BranchMisc: {
+      unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
+      Value |= BaseOpcode << 4;
+      Value |= 0x12fff << 8;
+
+      if (opcode == ARM::BX_RET)
+        op = 0xe;
+      else 
+        op = getMachineOpValue(MI,0);
+      Value |= op;
+
+      break;
+    }
+    case ARMII::Pseudo:
+      break;
+    }
+
+    break;
+  }
+  case ARMII::AddrMode1: {
+    unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
+    Value |= BaseOpcode << 21;
+
+    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    if (Format == ARMII::DPRdMisc) {
+      Value |= getMachineOpValue(MI,0) << 12;
+      Value |= getMachineOpValue(MI,1);
+      switch(opcode) {
+      case ARM::MOVsra_flag: {
+        Value |= 0x1 << 6;
+        Value |= 0x1 << 7;
+        break;
+      }
+      case ARM::MOVsrl_flag: {
+        Value |= 0x1 << 5;
+        Value |= 0x1 << 7;
+        break;
+      }
+      case ARM::MOVrx: {
+        Value |= 0x3 << 5;
+        break;
+      }
+      }
+      break;
+    }
+
+    bool IsDataProcessing3 = false;
+
+    if (Format == ARMII::DPRImS || Format == ARMII::DPRRegS ||
+        Format == ARMII::DPRSoRegS) {
+      Value |= 1 << 20;
+      IsDataProcessing3 = true;
+    }
+
+    bool IsDataProcessing1 = Format == ARMII::DPRdIm    ||
+                             Format == ARMII::DPRdReg   ||
+                             Format == ARMII::DPRdSoReg;
+    bool IsDataProcessing2 = Format == ARMII::DPRnIm    ||
+                             Format == ARMII::DPRnReg   ||
+                             Format == ARMII::DPRnSoReg;
+    IsDataProcessing3 = Format == ARMII::DPRIm     ||
+                        Format == ARMII::DPRReg    ||
+                        Format == ARMII::DPRSoReg  ||
+                        IsDataProcessing3;
+
+    // set first operand
+    op = getMachineOpValue(MI,0);
+    if (IsDataProcessing1 || IsDataProcessing3) {
+      Value |= op << 12;
+    } else if (IsDataProcessing2) {
+      Value |= op << 16;
+    }
+
+    if (IsDataProcessing3) {
+      op = getMachineOpValue(MI,1);
+      Value |= op << 16;
+    }
+
+    unsigned OperandIndex = IsDataProcessing3 ? 2 : 1;
+    // set shift operand
+    switch (Format) {
+    case ARMII::DPRdIm: case ARMII::DPRnIm:
+    case ARMII::DPRIm:  case ARMII::DPRImS: {
+      Value |= 1 << 25;
+      const MachineOperand &MO = MI.getOperand(OperandIndex);
+      op = ARM_AM::getSOImmVal(MO.getImmedValue());
+      Value |= op;
+
+      break;
+    }
+    case ARMII::DPRdReg: case ARMII::DPRnReg:
+    case ARMII::DPRReg:  case ARMII::DPRRegS: {
+      op = getMachineOpValue(MI,OperandIndex);
+      Value |= op;
+
+      break;
+    }
+    case ARMII::DPRdSoReg: case ARMII::DPRnSoReg:
+    case ARMII::DPRSoReg:  case ARMII::DPRSoRegS: {
+      op = getMachineOpValue(MI,OperandIndex);
+      Value |= op;
+
+      const MachineOperand &MO1 = MI.getOperand(OperandIndex + 1);
+      const MachineOperand &MO2 = MI.getOperand(OperandIndex + 2);
+      bool IsShiftByRegister = MO1.getReg() > 0;
+      switch(ARM_AM::getSORegShOp(MO2.getImmedValue())) {
+        default: assert(0 && "Unknown shift opc!");
+        case ARM_AM::asr: {
+          if(IsShiftByRegister)
+            Value |= 0x5 << 4;
+          else
+            Value |= 0x1 << 6;
+          break;
+        }
+        case ARM_AM::lsl: {
+          if(IsShiftByRegister)
+            Value |= 0x1 << 4;
+          break;
+        }
+        case ARM_AM::lsr: {
+          if(IsShiftByRegister)
+            Value |= 0x3 << 4;
+          else
+            Value |= 0x1 << 5;
+          break;
+        }
+        case ARM_AM::ror: {
+          if(IsShiftByRegister)
+            Value |= 0x7 << 4;
+          else
+            Value |= 0x3 << 5;
+          break;
+        }
+        case ARM_AM::rrx: {
+          Value |= 0x3 << 5;
+          break;
+        }
+      }
+      if(ARM_AM::getSORegShOp(MO2.getImmedValue()) != ARM_AM::rrx)
+        if(IsShiftByRegister) {
+          assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+          op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
+          assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
+          Value |= op << 8;
+        } else {
+          op = ARM_AM::getSORegOffset(MO2.getImm());
+          Value |= op << 7;
+        }
+      break;
+    }
+    default: assert(false && "Unknown operand type!");
+      break;
+    }
+
+    break;
+  }
+  case ARMII::AddrMode2: {
+    Value |= 1 << 26;
+
+    unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+    if (Index == ARMII::IndexModePre || Index == 0)
+      Value |= 1 << 24;
+    if (Index == ARMII::IndexModePre)
+      Value |= 1 << 21;
+
+    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    if (Format == ARMII::LdFrm)
+      Value |= 1 << 20;
+
+    unsigned BitByte = getBaseOpcodeFor(Desc);
+    Value |= BitByte << 22;
+
+    // set first operand
+    op = getMachineOpValue(MI,0);
+    Value |= op << 12;
+
+    // addressing mode
+    op = getMachineOpValue(MI,1);
+    Value |= op << 16;
+
+    const MachineOperand &MO2 = MI.getOperand(2);
+    const MachineOperand &MO3 = MI.getOperand(3);
+
+    Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) << 23;
+    if (!MO2.getReg()) { // is immediate
+      if (ARM_AM::getAM2Offset(MO3.getImm()))
+        Value |= ARM_AM::getAM2Offset(MO3.getImm());
+      break;
+    }
+
+    Value |= 1 << 25;
+    assert(MRegisterInfo::isPhysicalRegister(MO2.getReg()));
+    Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
+
+    if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
+      unsigned ShiftOp = getShiftOp(MO3);
+      Value |= ShiftOp << 5;
+      Value |= ShImm << 7;
+    }
+
+    break;
+  }
+  case ARMII::AddrMode3: {
+    unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+    if (Index == ARMII::IndexModePre || Index == 0)
+      Value |= 1 << 24;
+
+    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    if (Format == ARMII::LdFrm)
+      Value |= 1 << 20;
+
+    unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
+    Value |= BaseOpcode << 4;
+
+    // set first operand
+    op = getMachineOpValue(MI,0);
+    Value |= op << 12;
+
+    // addressing mode
+    op = getMachineOpValue(MI,1);
+    Value |= op << 16;
+
+    const MachineOperand &MO2 = MI.getOperand(2);
+    const MachineOperand &MO3 = MI.getOperand(3);
+
+    Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) << 23;
+
+    if (MO2.getReg()) {
+      Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
+      break;
+    }
+
+    if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
+      Value |= 1 << 22;
+      Value |= (ImmOffs >> 4) << 8; // immedH
+      Value |= (ImmOffs & ~0xF); // immedL
+    }
+
+    break;
+  }
+  case ARMII::AddrMode4: {
+    Value |= 1 << 27;
+
+    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    if (Format == ARMII::LdFrm)
+      Value |= 1 << 20;
+
+    unsigned OpIndex = 0;
+
+    // set first operand
+    op = getMachineOpValue(MI,OpIndex);
+    Value |= op << 16;
+
+    // set addressing mode
+    const MachineOperand &MO = MI.getOperand(OpIndex + 1);
+    ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
+    switch(Mode) {
+    default: assert(0 && "Unknown addressing sub-mode!");
+    case ARM_AM::ia: Value |= 0x1 << 23; break;
+    case ARM_AM::ib: Value |= 0x2 << 23; break;
+    case ARM_AM::da: break;
+    case ARM_AM::db: Value |= 0x1 << 24; break;
+    }
+
+    // set flag W
+    if (ARM_AM::getAM4WBFlag(MO.getImm()))
+      Value |= 0x1 << 21;
+
+    // set registers
+    for (unsigned i = OpIndex + 4, e = MI.getNumOperands(); i != e; ++i) {
+      const MachineOperand &MOR = MI.getOperand(i);
+      unsigned RegNumber = ARMRegisterInfo::getRegisterNumbering(MOR.getReg());
+      assert(MRegisterInfo::isPhysicalRegister(MOR.getReg()) && RegNumber < 16);
+      Value |= 0x1 << RegNumber;
+    }
+
+    break;
+  }
+  }
+
+  return Value;
 }
diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h
index 2c158b8..626c2b2 100644
--- a/lib/Target/ARM/ARMInstrInfo.h
+++ b/lib/Target/ARM/ARMInstrInfo.h
@@ -34,6 +34,7 @@ namespace ARMII {
     // so that we can tell if we forgot to set a value.
 
     AddrModeMask  = 0xf,
+    AddrModeNone  = 0,
     AddrMode1     = 1,
     AddrMode2     = 2,
     AddrMode3     = 3,
@@ -61,7 +62,54 @@ namespace ARMII {
     
     // Opcode
     OpcodeShift   = 9,
-    OpcodeMask    = 0xf << OpcodeShift
+    OpcodeMask    = 0xf << OpcodeShift,
+    
+    // Format
+    FormShift   = 13,
+    FormMask    = 31 << FormShift,
+
+// Pseudo instructions
+    Pseudo      = 1 << FormShift,
+
+// Multiply instructions
+    MulFrm      = 2 << FormShift,
+
+// Branch instructions
+    Branch      = 3 << FormShift,
+    BranchMisc  = 4 << FormShift,
+
+// Data Processing instructions
+    DPRdIm      = 5 << FormShift,
+    DPRdReg     = 6 << FormShift,
+    DPRdSoReg   = 7 << FormShift,
+    DPRdMisc    = 8 << FormShift,
+
+    DPRnIm      = 9 << FormShift,
+    DPRnReg     = 10 << FormShift,
+    DPRnSoReg   = 11 << FormShift,
+
+    DPRIm       = 12 << FormShift,
+    DPRReg      = 13 << FormShift,
+    DPRSoReg    = 14 << FormShift,
+
+    DPRImS      = 15 << FormShift,
+    DPRRegS     = 16 << FormShift,
+    DPRSoRegS   = 17 << FormShift,
+
+// Load and Store
+    LdFrm       = 18 << FormShift,
+    StFrm       = 19 << FormShift,
+
+// Miscellaneous arithmetic instructions
+    ArithMisc   = 20 << FormShift,
+
+// Thumb format
+    ThumbFrm    = 21 << FormShift,
+
+// VFP format
+    VPFFrm      = 22 << FormShift
+    
+
   };
 }
 
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 88da882..0a10eb1 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -330,6 +330,45 @@ def IndexModePre  : IndexMode<1>;
 def IndexModePost : IndexMode<2>;
 
 //===----------------------------------------------------------------------===//
+// ARM Instruction Format Definitions.
+//
+
+// Format specifies the encoding used by the instruction.  This is part of the
+// ad-hoc solution used to emit machine instruction encodings by our machine
+// code emitter.
+class Format<bits<5> val> {
+  bits<5> Value = val;
+}
+
+def Pseudo      : Format<1>;
+def MulFrm      : Format<2>;
+def Branch      : Format<3>;
+def BranchMisc  : Format<4>;
+
+def DPRdIm      : Format<5>;
+def DPRdReg     : Format<6>;
+def DPRdSoReg   : Format<7>;
+def DPRdMisc    : Format<8>;
+def DPRnIm      : Format<9>;
+def DPRnReg     : Format<10>;
+def DPRnSoReg   : Format<11>;
+def DPRIm       : Format<12>;
+def DPRReg      : Format<13>;
+def DPRSoReg    : Format<14>;
+def DPRImS      : Format<15>;
+def DPRRegS     : Format<16>;
+def DPRSoRegS   : Format<17>;
+
+def LdFrm       : Format<18>;
+def StFrm       : Format<19>;
+
+def ArithMisc   : Format<20>;
+def ThumbFrm    : Format<21>;
+def VFPFrm      : Format<22>;
+
+
+
+//===----------------------------------------------------------------------===//
 // ARM Instruction templates.
 //
 
@@ -345,7 +384,7 @@ class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
 }
 
 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
-              string cstr>
+              Format f, string cstr>
   : Instruction {
   let Namespace = "ARM";
 
@@ -359,11 +398,14 @@ class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
   IndexMode IM = im;
   bits<2> IndexModeBits = IM.Value;
   
+  Format F = f;
+  bits<5> Form = F.Value;
+  
   let Constraints = cstr;
 }
 
 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
-  : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ""> {
+  : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
   let OutOperandList = oops;
   let InOperandList = iops;
   let AsmString   = asm;
@@ -371,10 +413,9 @@ class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
 }
 
 // Almost all ARM instructions are predicable.
-class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
-        string opc, string asm, string cstr, list<dag> pattern>
-  // FIXME: Set all opcodes to 0 for now.
-  : InstARM<0, am, sz, im, cstr> {
+class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
+        Format f, string opc, string asm, string cstr, list<dag> pattern>
+  : InstARM<opcod, am, sz, im, f, cstr> {
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ops pred:$p));
   let AsmString   = !strconcat(opc, !strconcat("${p}", asm));
@@ -385,10 +426,9 @@ class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
 // Same as I except it can optionally modify CPSR. Note it's modeled as
 // an input operand since by default it's a zero register. It will
 // become an implicit def once it's "flipped".
-class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
-        string opc, string asm, string cstr, list<dag> pattern>
-  // FIXME: Set all opcodes to 0 for now.
-  : InstARM<0, am, sz, im, cstr> {
+class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
+         Format f, string opc, string asm, string cstr, list<dag> pattern>
+  : InstARM<opcod, am, sz, im, f, cstr> {
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
   let AsmString   = !strconcat(opc, !strconcat("${p}${s}", asm));
@@ -396,38 +436,58 @@ class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
   list<Predicate> Predicates = [IsARM];
 }
 
-class AI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm,"",pattern>;
-class AsI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, opc,asm,"",pattern>;
-class AI1<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AsI1<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AI2<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AI3<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AI4<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : I<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AI1x2<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, opc, asm, "", pattern>;
+class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+         string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
+      asm,"",pattern>;
+class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
+       asm,"",pattern>;
+class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
+class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+           string asm, list<dag> pattern>
+  : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
+       asm, "", pattern>;
+class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
+class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
+class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
+class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+            string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
 
 // Pre-indexed ops
-class AI2pr<dag oops, dag iops, string opc, string asm, string cstr,
-            list<dag> pattern>
-  : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
-class AI3pr<dag oops, dag iops, string opc, string asm, string cstr,
-            list<dag> pattern>
-  : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
+class AI2pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+            string asm, string cstr, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
+      asm, cstr, pattern>;
+class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+            string asm, string cstr, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
+      asm, cstr, pattern>;
 
 // Post-indexed ops
-class AI2po<dag oops, dag iops, string opc, string asm, string cstr,
-            list<dag> pattern>
-  : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, opc, asm, cstr,pattern>;
-class AI3po<dag oops, dag iops, string opc, string asm, string cstr,
-            list<dag> pattern>
-  : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, opc, asm, cstr,pattern>;
+class AI2po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+            string asm, string cstr, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
+      asm, cstr,pattern>;
+class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+            string asm, string cstr, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
+      asm, cstr,pattern>;
 
 
 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
@@ -436,28 +496,28 @@ class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
 
 /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
 /// binop that produces a value.
-multiclass AsI1_bin_irs<string opc, PatFrag opnode> {
-  def ri : AsI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
+multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
+  def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
                opc, " $dst, $a, $b",
                [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
-  def rr : AsI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
+  def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRReg,
                opc, " $dst, $a, $b",
                [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
-  def rs : AsI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
+  def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
                opc, " $dst, $a, $b",
                [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
 }
 
 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
 /// instruction modifies the CSPR register.
-multiclass ASI1_bin_s_irs<string opc, PatFrag opnode> {
-  def ri : AI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
+multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
+  def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRImS,
                opc, "s $dst, $a, $b",
                [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[], [CPSR]>;
-  def rr : AI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
+  def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRRegS,
                opc, "s $dst, $a, $b",
                [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[], [CPSR]>;
-  def rs : AI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
+  def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoRegS,
                opc, "s $dst, $a, $b",
                [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[], [CPSR]>;
 }
@@ -465,25 +525,25 @@ multiclass ASI1_bin_s_irs<string opc, PatFrag opnode> {
 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
 /// a explicit result, only implicitly set CPSR.
-multiclass AI1_cmp_irs<string opc, PatFrag opnode> {
-  def ri : AI1<(outs), (ins GPR:$a, so_imm:$b),
+multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
+  def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPRnIm,
                opc, " $a, $b",
                [(opnode GPR:$a, so_imm:$b)]>, Imp<[], [CPSR]>;
-  def rr : AI1<(outs), (ins GPR:$a, GPR:$b),
+  def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPRnReg,
                opc, " $a, $b",
                [(opnode GPR:$a, GPR:$b)]>, Imp<[], [CPSR]>;
-  def rs : AI1<(outs), (ins GPR:$a, so_reg:$b),
+  def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPRnSoReg,
                opc, " $a, $b",
                [(opnode GPR:$a, so_reg:$b)]>, Imp<[], [CPSR]>;
 }
 
 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
 /// register and one whose operand is a register rotated by 8/16/24.
-multiclass AI_unary_rrot<string opc, PatFrag opnode> {
-  def r     : AI<(outs GPR:$dst), (ins GPR:$Src),
+multiclass AI_unary_rrot<bits<4> opcod, string opc, PatFrag opnode> {
+  def r     : AI<opcod, (outs GPR:$dst), (ins GPR:$Src), Pseudo,
                  opc, " $dst, $Src",
                  [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
-  def r_rot : AI<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
+  def r_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo,
                  opc, " $dst, $Src, ror $rot",
                  [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
               Requires<[IsARM, HasV6]>;
@@ -491,23 +551,22 @@ multiclass AI_unary_rrot<string opc, PatFrag opnode> {
 
 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
 /// register and one whose operand is a register rotated by 8/16/24.
-multiclass AI_bin_rrot<string opc, PatFrag opnode> {
-  def rr     : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
-                  opc, " $dst, $LHS, $RHS",
+multiclass AI_bin_rrot<bits<4> opcod, string opc, PatFrag opnode> {
+  def rr     : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
+                  Pseudo, opc, " $dst, $LHS, $RHS",
                   [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
                   Requires<[IsARM, HasV6]>;
-  def rr_rot : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
-                  opc, " $dst, $LHS, $RHS, ror $rot",
+  def rr_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
+                  Pseudo, opc, " $dst, $LHS, $RHS, ror $rot",
                   [(set GPR:$dst, (opnode GPR:$LHS,
                                           (rotr GPR:$RHS, rot_imm:$rot)))]>,
                   Requires<[IsARM, HasV6]>;
 }
 
 // Special cases.
-class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
-         string asm, string cstr, list<dag> pattern>
-  // FIXME: Set all opcodes to 0 for now.
-  : InstARM<0, am, sz, im, cstr> {
+class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+         IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
+  : InstARM<opcod, am, sz, im, f, cstr> {
   let OutOperandList = oops;
   let InOperandList = iops;
   let AsmString   = asm;
@@ -515,39 +574,54 @@ class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
   list<Predicate> Predicates = [IsARM];
 }
 
-class AXI<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AXI1<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AXI2<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AXI3<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AXI4<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
-
-class AXIx2<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
+class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+          list<dag> pattern>
+  : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+           list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+           list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+           list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+           list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
+       "", pattern>;
+
+class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+            list<dag> pattern>
+  : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
+       "", pattern>;
 
 // BR_JT instructions
-class JTI<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>;
-class JTI1<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>;
-class JTI2<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>;
+class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
+       asm, "", pattern>;
+class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
+       asm, "", pattern>;
+class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
+       asm, "", pattern>;
 
 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
 /// setting carry bit. But it can optionally set CPSR.
-multiclass AsXI1_bin_c_irs<string opc, PatFrag opnode> {
-  def ri : AXI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
-               !strconcat(opc, "${s} $dst, $a, $b"),
+multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
+  def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
+                DPRIm, !strconcat(opc, "${s} $dst, $a, $b"),
                [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[CPSR], []>;
-  def rr : AXI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
-               !strconcat(opc, "${s} $dst, $a, $b"),
+  def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
+                DPRReg, !strconcat(opc, "${s} $dst, $a, $b"),
                [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[CPSR], []>;
-  def rs : AXI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
-               !strconcat(opc, "${s} $dst, $a, $b"),
+  def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
+                DPRSoReg, !strconcat(opc, "${s} $dst, $a, $b"),
                [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[CPSR], []>;
 }
 
@@ -590,50 +664,50 @@ PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
            [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
 
 let isNotDuplicable = 1 in {
-def PICADD : AXI1<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
-                   "$cp:\n\tadd$p $dst, pc, $a",
+def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
+                  Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
                    [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
 
 let isLoad = 1, AddedComplexity = 10 in {
-def PICLD   : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
-                  "${addr:label}:\n\tldr$p $dst, $addr",
+def PICLD   : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+                  Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
                   [(set GPR:$dst, (load addrmodepc:$addr))]>;
 
-def PICLDZH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
-                  "${addr:label}:\n\tldr${p}h $dst, $addr",
+def PICLDZH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+                  Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
                   [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
 
-def PICLDZB : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
-                  "${addr:label}:\n\tldr${p}b $dst, $addr",
+def PICLDZB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+                  Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
                   [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
 
-def PICLDH  : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
-                  "${addr:label}:\n\tldr${p}h $dst, $addr",
+def PICLDH  : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+                  Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
                   [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
 
-def PICLDB  : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
-                  "${addr:label}:\n\tldr${p}b $dst, $addr",
+def PICLDB  : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+                  Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
                   [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
 
-def PICLDSH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
-                  "${addr:label}:\n\tldr${p}sh $dst, $addr",
+def PICLDSH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+                  Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
                   [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
 
-def PICLDSB : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
-                  "${addr:label}:\n\tldr${p}sb $dst, $addr",
+def PICLDSB : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+                  Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
                   [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
 }
 let isStore = 1, AddedComplexity = 10 in {
-def PICSTR  : AXI2<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
-               "${addr:label}:\n\tstr$p $src, $addr",
+def PICSTR  : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
+               Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
                [(store GPR:$src, addrmodepc:$addr)]>;
 
-def PICSTRH : AXI3<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
-               "${addr:label}:\n\tstr${p}h $src, $addr",
+def PICSTRH : AXI3<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
+               Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
                [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
 
-def PICSTRB : AXI2<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
-               "${addr:label}:\n\tstr${p}b $src, $addr",
+def PICSTRB : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
+               Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
                [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
 }
 }
@@ -643,37 +717,37 @@ def PICSTRB : AXI2<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
 //
 
 let isReturn = 1, isTerminator = 1 in
-  def BX_RET : AI<(outs), (ins), "bx", " lr", [(ARMretflag)]>;
+  def BX_RET : AI<0x1, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]>;
 
 // FIXME: remove when we have a way to marking a MI with these properties.
 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
 // operand list.
 let isLoad = 1, isReturn = 1, isTerminator = 1 in
-  def LDM_RET : AXI4<(outs),
+  def LDM_RET : AXI4<0x0, (outs),
                     (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
-                    "ldm${p}${addr:submode} $addr, $dst1",
+                    LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
                     []>;
 
 let isCall = 1,
   Defs = [R0, R1, R2, R3, R12, LR,
           D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
-  def BL  : AXI<(outs), (ins i32imm:$func, variable_ops),
+  def BL  : AXI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch,
                 "bl ${func:call}",
                 [(ARMcall tglobaladdr:$func)]>;
 
-  def BL_pred : AI<(outs), (ins i32imm:$func, variable_ops),
-                    "bl", " ${func:call}",
-                    [(ARMcall_pred tglobaladdr:$func)]>;
+  def BL_pred : AI<0xB, (outs), (ins i32imm:$func, variable_ops),
+                   Branch, "bl", " ${func:call}",
+                   [(ARMcall_pred tglobaladdr:$func)]>;
 
   // ARMv5T and above
-  def BLX : AXI<(outs), (ins GPR:$func, variable_ops),
+  def BLX : AXI<0x2, (outs), (ins GPR:$func, variable_ops), BranchMisc,
                 "blx $func",
                 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>;
   let Uses = [LR] in {
     // ARMv4T
-    def BX : AXIx2<(outs), (ins GPR:$func, variable_ops),
-                  "mov lr, pc\n\tbx $func",
-                  [(ARMcall_nolink GPR:$func)]>;
+    def BX : AXIx2<0x0, (outs), (ins GPR:$func, variable_ops),
+                   BranchMisc, "mov lr, pc\n\tbx $func",
+                   [(ARMcall_nolink GPR:$func)]>;
   }
 }
 
@@ -681,18 +755,18 @@ let isBranch = 1, isTerminator = 1 in {
   // B is "predicable" since it can be xformed into a Bcc.
   let isBarrier = 1 in {
     let isPredicable = 1 in
-    def B : AXI<(outs), (ins brtarget:$target), "b $target",
+    def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b $target",
                 [(br bb:$target)]>;
 
   let isNotDuplicable = 1 in {
-  def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
+  def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
                     "mov pc, $target \n$jt",
                     [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
-  def BR_JTm : JTI2<(outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
+  def BR_JTm : JTI2<0x0, (outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
                      "ldr pc, $target \n$jt",
                      [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
                        imm:$id)]>;
-  def BR_JTadd : JTI1<(outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
+  def BR_JTadd : JTI1<0x0, (outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
                        i32imm:$id),
                        "add pc, $target, $idx \n$jt",
                        [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
@@ -702,8 +776,9 @@ let isBranch = 1, isTerminator = 1 in {
 
   // FIXME: should be able to write a pattern for ARMBrcond, but can't use
   // a two-value operand where a dag node expects two operands. :( 
-  def Bcc : AI<(outs), (ins brtarget:$target), "b", " $target",
-                [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
+  def Bcc : AI<0x0, (outs), (ins brtarget:$target), Branch,
+               "b", " $target",
+               [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -712,123 +787,133 @@ let isBranch = 1, isTerminator = 1 in {
 
 // Load
 let isLoad = 1 in {
-def LDR  : AI2<(outs GPR:$dst), (ins addrmode2:$addr),
+def LDR  : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
                "ldr", " $dst, $addr",
                [(set GPR:$dst, (load addrmode2:$addr))]>;
 
 // Special LDR for loads from non-pc-relative constpools.
 let isReMaterializable = 1 in
-def LDRcp : AI2<(outs GPR:$dst), (ins addrmode2:$addr),
+def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
                  "ldr", " $dst, $addr", []>;
 
 // Loads with zero extension
-def LDRH  : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
+def LDRH  : AI3<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
                  "ldr", "h $dst, $addr",
                 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
 
-def LDRB  : AI2<(outs GPR:$dst), (ins addrmode2:$addr),
+def LDRB  : AI2<0x1, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
                  "ldr", "b $dst, $addr",
                 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
 
 // Loads with sign extension
-def LDRSH : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
+def LDRSH : AI3<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
                  "ldr", "sh $dst, $addr",
                 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
 
-def LDRSB : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
+def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
                  "ldr", "sb $dst, $addr",
                 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
 
 // Load doubleword
-def LDRD  : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
+def LDRD  : AI3<0x0, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
                  "ldr", "d $dst, $addr",
                 []>, Requires<[IsARM, HasV5T]>;
 
 // Indexed loads
-def LDR_PRE  : AI2pr<(outs GPR:$dst, GPR:$base_wb), (ins addrmode2:$addr),
-                    "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
+def LDR_PRE  : AI2pr<0x0, (outs GPR:$dst, GPR:$base_wb),
+                     (ins addrmode2:$addr), LdFrm,
+                     "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
 
-def LDR_POST : AI2po<(outs GPR:$dst, GPR:$base_wb), (ins GPR:$base, am2offset:$offset),
-                    "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
+def LDR_POST : AI2po<0x0, (outs GPR:$dst, GPR:$base_wb),
+                     (ins GPR:$base, am2offset:$offset), LdFrm,
+                     "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
 
-def LDRH_PRE  : AI3pr<(outs GPR:$dst, GPR:$base_wb), (ins addrmode3:$addr),
+def LDRH_PRE  : AI3pr<0xB, (outs GPR:$dst, GPR:$base_wb),
+                     (ins addrmode3:$addr), LdFrm,
                      "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
 
-def LDRH_POST : AI3po<(outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am3offset:$offset),
+def LDRH_POST : AI3po<0xB, (outs GPR:$dst, GPR:$base_wb),
+                     (ins GPR:$base,am3offset:$offset), LdFrm,
                      "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
 
-def LDRB_PRE  : AI2pr<(outs GPR:$dst, GPR:$base_wb), (ins addrmode2:$addr),
+def LDRB_PRE  : AI2pr<0x1, (outs GPR:$dst, GPR:$base_wb),
+                     (ins addrmode2:$addr), LdFrm,
                      "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
 
-def LDRB_POST : AI2po<(outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am2offset:$offset),
+def LDRB_POST : AI2po<0x1, (outs GPR:$dst, GPR:$base_wb),
+                     (ins GPR:$base,am2offset:$offset), LdFrm,
                      "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
 
-def LDRSH_PRE : AI3pr<(outs GPR:$dst, GPR:$base_wb), (ins addrmode3:$addr),
+def LDRSH_PRE : AI3pr<0xE, (outs GPR:$dst, GPR:$base_wb),
+                      (ins addrmode3:$addr), LdFrm,
                       "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
 
-def LDRSH_POST: AI3po<(outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am3offset:$offset),
+def LDRSH_POST: AI3po<0xE, (outs GPR:$dst, GPR:$base_wb),
+                      (ins GPR:$base,am3offset:$offset), LdFrm,
                       "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
 
-def LDRSB_PRE : AI3pr<(outs GPR:$dst, GPR:$base_wb), (ins addrmode3:$addr),
+def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb),
+                      (ins addrmode3:$addr), LdFrm,
                       "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
 
-def LDRSB_POST: AI3po<(outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am3offset:$offset),
+def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
+                      (ins GPR:$base,am3offset:$offset), LdFrm,
                       "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
 } // isLoad
 
 // Store
 let isStore = 1 in {
-def STR  : AI2<(outs), (ins GPR:$src, addrmode2:$addr),
+def STR  : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
                "str", " $src, $addr",
                [(store GPR:$src, addrmode2:$addr)]>;
 
 // Stores with truncate
-def STRH : AI3<(outs), (ins GPR:$src, addrmode3:$addr),
+def STRH : AI3<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
                "str", "h $src, $addr",
                [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
 
-def STRB : AI2<(outs), (ins GPR:$src, addrmode2:$addr),
+def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
                "str", "b $src, $addr",
                [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
 
 // Store doubleword
-def STRD : AI3<(outs), (ins GPR:$src, addrmode3:$addr),
+def STRD : AI3<0x0, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
                "str", "d $src, $addr",
                []>, Requires<[IsARM, HasV5T]>;
 
 // Indexed stores
-def STR_PRE  : AI2pr<(outs GPR:$base_wb),
-                     (ins GPR:$src, GPR:$base, am2offset:$offset),
+def STR_PRE  : AI2pr<0x0, (outs GPR:$base_wb),
+                     (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
                     "str", " $src, [$base, $offset]!", "$base = $base_wb",
                     [(set GPR:$base_wb,
                       (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
 
-def STR_POST : AI2po<(outs GPR:$base_wb),
-                     (ins GPR:$src, GPR:$base,am2offset:$offset),
+def STR_POST : AI2po<0x0, (outs GPR:$base_wb),
+                     (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
                     "str", " $src, [$base], $offset", "$base = $base_wb",
                     [(set GPR:$base_wb,
                       (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
 
-def STRH_PRE : AI3pr<(outs GPR:$base_wb),
-                     (ins GPR:$src, GPR:$base,am3offset:$offset),
+def STRH_PRE : AI3pr<0xB, (outs GPR:$base_wb),
+                     (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
                      "str", "h $src, [$base, $offset]!", "$base = $base_wb",
                     [(set GPR:$base_wb,
                       (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
 
-def STRH_POST: AI3po<(outs GPR:$base_wb),
-                     (ins GPR:$src, GPR:$base,am3offset:$offset),
+def STRH_POST: AI3po<0xB, (outs GPR:$base_wb),
+                     (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
                      "str", "h $src, [$base], $offset", "$base = $base_wb",
                     [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
                                          GPR:$base, am3offset:$offset))]>;
 
-def STRB_PRE : AI2pr<(outs GPR:$base_wb),
-                     (ins GPR:$src, GPR:$base,am2offset:$offset),
+def STRB_PRE : AI2pr<0x1, (outs GPR:$base_wb),
+                     (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
                      "str", "b $src, [$base, $offset]!", "$base = $base_wb",
                     [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
                                          GPR:$base, am2offset:$offset))]>;
 
-def STRB_POST: AI2po<(outs GPR:$base_wb),
-                     (ins GPR:$src, GPR:$base,am2offset:$offset),
+def STRB_POST: AI2po<0x1, (outs GPR:$base_wb),
+                     (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
                      "str", "b $src, [$base], $offset", "$base = $base_wb",
                     [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
                                          GPR:$base, am2offset:$offset))]>;
@@ -840,41 +925,41 @@ def STRB_POST: AI2po<(outs GPR:$base_wb),
 
 // FIXME: $dst1 should be a def.
 let isLoad = 1 in
-def LDM : AXI4<(outs),
+def LDM : AXI4<0x0, (outs),
                (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
-               "ldm${p}${addr:submode} $addr, $dst1",
+               LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
                []>;
 
 let isStore = 1 in
-def STM : AXI4<(outs),
+def STM : AXI4<0x0, (outs),
                (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
-               "stm${p}${addr:submode} $addr, $src1",
+               StFrm, "stm${p}${addr:submode} $addr, $src1",
                []>;
 
 //===----------------------------------------------------------------------===//
 //  Move Instructions.
 //
 
-def MOVr : AsI1<(outs GPR:$dst), (ins GPR:$src),
+def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
                  "mov", " $dst, $src", []>;
-def MOVs : AsI1<(outs GPR:$dst), (ins so_reg:$src),
+def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
                  "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
 
 let isReMaterializable = 1 in
-def MOVi : AsI1<(outs GPR:$dst), (ins so_imm:$src),
+def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm,
                  "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
 
-def MOVrx : AsI1<(outs GPR:$dst), (ins GPR:$src),
+def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
                  "mov", " $dst, $src, rrx",
                  [(set GPR:$dst, (ARMrrx GPR:$src))]>;
 
 // These aren't really mov instructions, but we have to define them this way
 // due to flag operands.
 
-def MOVsrl_flag : AI1<(outs GPR:$dst), (ins GPR:$src),
+def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
                       "mov", "s $dst, $src, lsr #1",
                       [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, Imp<[], [CPSR]>;
-def MOVsra_flag : AI1<(outs GPR:$dst), (ins GPR:$src),
+def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
                       "mov", "s $dst, $src, asr #1",
                       [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, Imp<[], [CPSR]>;
 
@@ -884,12 +969,12 @@ def MOVsra_flag : AI1<(outs GPR:$dst), (ins GPR:$src),
 
 // Sign extenders
 
-defm SXTB  : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
-defm SXTH  : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
+defm SXTB  : AI_unary_rrot<0x0, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
+defm SXTH  : AI_unary_rrot<0x0, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
 
-defm SXTAB : AI_bin_rrot<"sxtab",
+defm SXTAB : AI_bin_rrot<0x0, "sxtab",
                         BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
-defm SXTAH : AI_bin_rrot<"sxtah",
+defm SXTAH : AI_bin_rrot<0x0, "sxtah",
                         BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
 
 // TODO: SXT(A){B|H}16
@@ -897,18 +982,18 @@ defm SXTAH : AI_bin_rrot<"sxtah",
 // Zero extenders
 
 let AddedComplexity = 16 in {
-defm UXTB   : AI_unary_rrot<"uxtb"  , UnOpFrag<(and node:$Src, 0x000000FF)>>;
-defm UXTH   : AI_unary_rrot<"uxth"  , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
-defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
+defm UXTB   : AI_unary_rrot<0x0, "uxtb"  , UnOpFrag<(and node:$Src, 0x000000FF)>>;
+defm UXTH   : AI_unary_rrot<0x0, "uxth"  , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
+defm UXTB16 : AI_unary_rrot<0x0, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
 
 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
                (UXTB16r_rot GPR:$Src, 24)>;
 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
                (UXTB16r_rot GPR:$Src, 8)>;
 
-defm UXTAB : AI_bin_rrot<"uxtab",
+defm UXTAB : AI_bin_rrot<0x0, "uxtab",
                         BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
-defm UXTAH : AI_bin_rrot<"uxtah",
+defm UXTAH : AI_bin_rrot<0x0, "uxtah",
                         BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
 }
 
@@ -921,40 +1006,40 @@ defm UXTAH : AI_bin_rrot<"uxtah",
 //  Arithmetic Instructions.
 //
 
-defm ADD  : AsI1_bin_irs<"add", BinOpFrag<(add  node:$LHS, node:$RHS)>>;
-defm SUB  : AsI1_bin_irs<"sub", BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
+defm ADD  : AsI1_bin_irs<0x4, "add", BinOpFrag<(add  node:$LHS, node:$RHS)>>;
+defm SUB  : AsI1_bin_irs<0x2, "sub", BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
 
 // ADD and SUB with 's' bit set.
-defm ADDS : ASI1_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
-defm SUBS : ASI1_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
+defm ADDS : ASI1_bin_s_irs<0x4, "add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
+defm SUBS : ASI1_bin_s_irs<0x2, "sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
 
 // FIXME: Do not allow ADC / SBC to be predicated for now.
-defm ADC  : AsXI1_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
-defm SBC  : AsXI1_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
+defm ADC  : AsXI1_bin_c_irs<0x5, "adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
+defm SBC  : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
 
 // These don't define reg/reg forms, because they are handled above.
-def RSBri : AsI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
+def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
                   "rsb", " $dst, $a, $b",
                   [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
 
-def RSBrs : AsI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
+def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
                   "rsb", " $dst, $a, $b",
                   [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
 
 // RSB with 's' bit set.
-def RSBSri : AI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
+def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
                  "rsb", "s $dst, $a, $b",
                  [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>, Imp<[], [CPSR]>;
-def RSBSrs : AI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
+def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
                  "rsb", "s $dst, $a, $b",
                  [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>, Imp<[], [CPSR]>;
 
 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
-def RSCri : AXI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
-                 "rsc${s} $dst, $a, $b",
+def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
+                 DPRIm, "rsc${s} $dst, $a, $b",
                  [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, Imp<[CPSR], []>;
-def RSCrs : AXI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
-                 "rsc${s} $dst, $a, $b",
+def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
+                 DPRSoReg, "rsc${s} $dst, $a, $b",
                  [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, Imp<[CPSR], []>;
 
 // (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
@@ -977,17 +1062,17 @@ def : ARMPat<(add    GPR:$src, so_imm_neg:$imm),
 //  Bitwise Instructions.
 //
 
-defm AND   : AsI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
-defm ORR   : AsI1_bin_irs<"orr", BinOpFrag<(or  node:$LHS, node:$RHS)>>;
-defm EOR   : AsI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
-defm BIC   : AsI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
+defm AND   : AsI1_bin_irs<0x0, "and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
+defm ORR   : AsI1_bin_irs<0xC, "orr", BinOpFrag<(or  node:$LHS, node:$RHS)>>;
+defm EOR   : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
+defm BIC   : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
 
-def  MVNr  : AsI<(outs GPR:$dst), (ins GPR:$src),
+def  MVNr  : AsI<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
                  "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
-def  MVNs  : AsI<(outs GPR:$dst), (ins so_reg:$src),
+def  MVNs  : AsI<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
                  "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
 let isReMaterializable = 1 in
-def  MVNi  : AsI<(outs GPR:$dst), (ins so_imm:$imm),
+def  MVNi  : AsI<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
                  "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
 
 def : ARMPat<(and   GPR:$src, so_imm_not:$imm),
@@ -997,119 +1082,119 @@ def : ARMPat<(and   GPR:$src, so_imm_not:$imm),
 //  Multiply Instructions.
 //
 
-def MUL  : AsI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
-                "mul", " $dst, $a, $b",
-                [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
+def MUL  : AsI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
+               "mul", " $dst, $a, $b",
+               [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
 
-def MLA  : AsI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
-                "mla", " $dst, $a, $b, $c",
-                [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
+def MLA  : AsI<0x2, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
+               MulFrm, "mla", " $dst, $a, $b, $c",
+               [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
 
 // Extra precision multiplies with low / high results
-def SMULL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
-                "smull", " $ldst, $hdst, $a, $b", []>;
+def SMULL : AsI<0xC, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
+                MulFrm, "smull", " $ldst, $hdst, $a, $b", []>;
 
-def UMULL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
-                "umull", " $ldst, $hdst, $a, $b", []>;
+def UMULL : AsI<0x8, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
+                MulFrm, "umull", " $ldst, $hdst, $a, $b", []>;
 
 // Multiply + accumulate
-def SMLAL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
-                "smlal", " $ldst, $hdst, $a, $b", []>;
+def SMLAL : AsI<0xE, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
+                MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>;
 
-def UMLAL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
-                "umlal", " $ldst, $hdst, $a, $b", []>;
+def UMLAL : AsI<0xA, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
+                MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>;
 
-def UMAAL : AI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
+def UMAAL : AI<0x0, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), MulFrm,
                "umaal", " $ldst, $hdst, $a, $b", []>,
             Requires<[IsARM, HasV6]>;
 
 // Most significant word multiply
-def SMMUL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
+def SMMUL : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
                "smmul", " $dst, $a, $b",
                [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
             Requires<[IsARM, HasV6]>;
 
-def SMMLA : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
+def SMMLA : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
                "smmla", " $dst, $a, $b, $c",
                [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
             Requires<[IsARM, HasV6]>;
 
 
-def SMMLS : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
+def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
                "smmls", " $dst, $a, $b, $c",
                [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
                Requires<[IsARM, HasV6]>;
 
-multiclass AI_smul<string opc, PatFrag opnode> {
-  def BB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
+multiclass AI_smul<bits<4> opcod, string opc, PatFrag opnode> {
+  def BB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
               !strconcat(opc, "bb"), " $dst, $a, $b",
               [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
                                       (sext_inreg GPR:$b, i16)))]>,
            Requires<[IsARM, HasV5TE]>;
-  def BT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
+  def BT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
               !strconcat(opc, "bt"), " $dst, $a, $b",
               [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
                                       (sra GPR:$b, 16)))]>,
            Requires<[IsARM, HasV5TE]>;
-  def TB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
+  def TB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
               !strconcat(opc, "tb"), " $dst, $a, $b",
               [(set GPR:$dst, (opnode (sra GPR:$a, 16),
                                       (sext_inreg GPR:$b, i16)))]>,
            Requires<[IsARM, HasV5TE]>;
-  def TT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
+  def TT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
               !strconcat(opc, "tt"), " $dst, $a, $b",
               [(set GPR:$dst, (opnode (sra GPR:$a, 16),
                                       (sra GPR:$b, 16)))]>,
             Requires<[IsARM, HasV5TE]>;
-  def WB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
+  def WB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
               !strconcat(opc, "wb"), " $dst, $a, $b",
               [(set GPR:$dst, (sra (opnode GPR:$a,
                                     (sext_inreg GPR:$b, i16)), 16))]>,
            Requires<[IsARM, HasV5TE]>;
-  def WT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
+  def WT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
               !strconcat(opc, "wt"), " $dst, $a, $b",
               [(set GPR:$dst, (sra (opnode GPR:$a,
                                     (sra GPR:$b, 16)), 16))]>,
             Requires<[IsARM, HasV5TE]>;
 }
 
-multiclass AI_smla<string opc, PatFrag opnode> {
-  def BB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
+multiclass AI_smla<bits<4> opcod, string opc, PatFrag opnode> {
+  def BB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
               !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
               [(set GPR:$dst, (add GPR:$acc,
                                (opnode (sext_inreg GPR:$a, i16),
                                        (sext_inreg GPR:$b, i16))))]>,
            Requires<[IsARM, HasV5TE]>;
-  def BT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
+  def BT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
               !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
               [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
                                                      (sra GPR:$b, 16))))]>,
            Requires<[IsARM, HasV5TE]>;
-  def TB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
+  def TB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
               !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
               [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
                                                  (sext_inreg GPR:$b, i16))))]>,
            Requires<[IsARM, HasV5TE]>;
-  def TT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
+  def TT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
               !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
               [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
                                                      (sra GPR:$b, 16))))]>,
             Requires<[IsARM, HasV5TE]>;
 
-  def WB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
+  def WB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
               !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
               [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
                                             (sext_inreg GPR:$b, i16)), 16)))]>,
            Requires<[IsARM, HasV5TE]>;
-  def WT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
+  def WT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
               !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
               [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
                                                    (sra GPR:$b, 16)), 16)))]>,
             Requires<[IsARM, HasV5TE]>;
 }
 
-defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
-defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
+defm SMUL : AI_smul<0x0, "smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
+defm SMLA : AI_smla<0x0, "smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
 
 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
@@ -1118,15 +1203,15 @@ defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
 //  Misc. Arithmetic Instructions.
 //
 
-def CLZ  : AI<(outs GPR:$dst), (ins GPR:$src),
+def CLZ  : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
               "clz", " $dst, $src",
               [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
 
-def REV  : AI<(outs GPR:$dst), (ins GPR:$src),
+def REV  : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
               "rev", " $dst, $src",
               [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
 
-def REV16 : AI<(outs GPR:$dst), (ins GPR:$src),
+def REV16 : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
                "rev16", " $dst, $src",
                [(set GPR:$dst,
                    (or (and (srl GPR:$src, 8), 0xFF),
@@ -1135,7 +1220,7 @@ def REV16 : AI<(outs GPR:$dst), (ins GPR:$src),
                                (and (shl GPR:$src, 8), 0xFF000000)))))]>,
                Requires<[IsARM, HasV6]>;
 
-def REVSH : AI<(outs GPR:$dst), (ins GPR:$src),
+def REVSH : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
                "revsh", " $dst, $src",
                [(set GPR:$dst,
                   (sext_inreg
@@ -1143,8 +1228,8 @@ def REVSH : AI<(outs GPR:$dst), (ins GPR:$src),
                         (shl GPR:$src, 8)), i16))]>,
                Requires<[IsARM, HasV6]>;
 
-def PKHBT : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
-               "pkhbt", " $dst, $src1, $src2, LSL $shamt",
+def PKHBT : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
+               Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
                [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
                                    (and (shl GPR:$src2, (i32 imm:$shamt)),
                                         0xFFFF0000)))]>,
@@ -1157,8 +1242,8 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
                (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
 
 
-def PKHTB : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
-               "pkhtb", " $dst, $src1, $src2, ASR $shamt",
+def PKHTB : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
+               Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
                [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
                                    (and (sra GPR:$src2, imm16_31:$shamt),
                                         0xFFFF)))]>, Requires<[IsARM, HasV6]>;
@@ -1176,15 +1261,21 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
 //  Comparison Instructions...
 //
 
-defm CMP  : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
-defm CMN  : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
+defm CMP  : AI1_cmp_irs<0xA, "cmp",
+                        BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
+defm CMN  : AI1_cmp_irs<0xB, "cmn",
+                        BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
 
 // Note that TST/TEQ don't set all the same flags that CMP does!
-defm TST  : AI1_cmp_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
-defm TEQ  : AI1_cmp_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
+defm TST  : AI1_cmp_irs<0x8, "tst",
+                        BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
+defm TEQ  : AI1_cmp_irs<0x9, "teq",
+                        BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
 
-defm CMPnz : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
-defm CMNnz : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
+defm CMPnz : AI1_cmp_irs<0xA, "cmp",
+                         BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
+defm CMNnz : AI1_cmp_irs<0xA, "cmn",
+                         BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
 
 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
              (CMNri  GPR:$src, so_imm_neg:$imm)>;
@@ -1196,32 +1287,33 @@ def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
 // Conditional moves
 // FIXME: should be able to write a pattern for ARMcmov, but can't use
 // a two-value operand where a dag node expects two operands. :( 
-def MOVCCr : AI<(outs GPR:$dst), (ins GPR:$false, GPR:$true),
-                "mov", " $dst, $true",
+def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true),
+                DPRdReg, "mov", " $dst, $true",
       [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
                 RegConstraint<"$false = $dst">;
 
-def MOVCCs : AI<(outs GPR:$dst), (ins GPR:$false, so_reg:$true),
-                "mov", " $dst, $true",
+def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true),
+                DPRdSoReg, "mov", " $dst, $true",
    [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
                 RegConstraint<"$false = $dst">;
 
-def MOVCCi : AI<(outs GPR:$dst), (ins GPR:$false, so_imm:$true),
-                "mov", " $dst, $true",
+def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true),
+                DPRdIm, "mov", " $dst, $true",
    [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
                 RegConstraint<"$false = $dst">;
 
 
 // LEApcrel - Load a pc-relative address into a register without offending the
 // assembler.
-def LEApcrel : AXI1<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
+def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
                    !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
                                          "${:private}PCRELL${:uid}+8))\n"),
                               !strconcat("${:private}PCRELL${:uid}:\n\t",
                                          "add$p $dst, pc, #PCRELV${:uid}")),
                    []>;
 
-def LEApcrelJT : AXI1<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
+def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
+          Pseudo,
           !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
                                          "${:private}PCRELL${:uid}+8))\n"),
                               !strconcat("${:private}PCRELL${:uid}:\n\t",
@@ -1235,7 +1327,7 @@ def LEApcrelJT : AXI1<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
 // __aeabi_read_tp preserves the registers r1-r3.
 let isCall = 1,
   Defs = [R0, R12, LR, CPSR] in {
-  def TPsoft : AXI<(outs), (ins),
+  def TPsoft : AXI<0x0, (outs), (ins), BranchMisc,
                "bl __aeabi_read_tp",
                [(set R0, ARMthread_pointer)]>;
 }
@@ -1254,7 +1346,7 @@ def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
 
 // Two piece so_imms.
 let isReMaterializable = 1 in
-def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
+def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc,
                          "mov", " $dst, $src",
                          [(set GPR:$dst, so_imm2part:$src)]>;
 
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 0639ef5..278d182 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -32,7 +32,7 @@ class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
              string asm, string cstr, list<dag> pattern>
   // FIXME: Set all opcodes to 0 for now.
-  : InstARM<0, am, sz, IndexModeNone, cstr> {
+  : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
   let OutOperandList = outs;
   let InOperandList = ins;
   let AsmString   = asm;
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index c89c9640..4fca605 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -17,44 +17,50 @@
 
 // ARM Float Instruction
 class ASI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
-  : AI<outs, ins, opc, asm, pattern> {
+  : AI<0x0, outs, ins, VFPFrm, opc, asm, pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
 }
 
 class ASI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
-  : I<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, opc, asm, "", pattern> {
+  : I<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
+      VFPFrm, opc, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
 }
 
 // ARM Double Instruction
 class ADI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
-  : AI<outs, ins, opc, asm, pattern> {
+  : AI<0x0, outs, ins, VFPFrm, opc, asm, pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
 }
 
 class ADI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
-  : I<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, opc, asm, "", pattern> {
+  : I<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
+      VFPFrm, opc, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
 }
 
 // Special cases.
 class AXSI<dag outs, dag ins, string asm, list<dag> pattern>
-  : XI<outs, ins, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern> {
+  : XI<0x0, outs, ins, AddrModeNone, Size4Bytes, IndexModeNone,
+       VFPFrm, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
 }
 
 class AXSI5<dag outs, dag ins, string asm, list<dag> pattern>
-  : XI<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
+  : XI<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
+       VFPFrm, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
 }
 
 class AXDI<dag outs, dag ins, string asm, list<dag> pattern>
-  : XI<outs, ins, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern> {
+  : XI<0x0, outs, ins, AddrModeNone, Size4Bytes, IndexModeNone,
+       VFPFrm, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
 }
 
 class AXDI5<dag outs, dag ins, string asm, list<dag> pattern>
-  : XI<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
+  : XI<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
+       VFPFrm, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
 }
 
diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp
index 294a12b..9622a29 100644
--- a/lib/Target/ARM/ARMJITInfo.cpp
+++ b/lib/Target/ARM/ARMJITInfo.cpp
@@ -127,5 +127,23 @@ void *ARMJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
 /// referenced global symbols.
 void ARMJITInfo::relocate(void *Function, MachineRelocation *MR,
                           unsigned NumRelocs, unsigned char* GOTBase) {
-
+  for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
+    void *RelocPos = (char*)Function + MR->getMachineCodeOffset();
+    intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
+    switch ((ARM::RelocationType)MR->getRelocationType()) {
+    case ARM::reloc_arm_relative: {
+      // PC relative relocation
+      *((unsigned*)RelocPos) += (unsigned)ResultPtr;
+      break;
+    }
+    case ARM::reloc_arm_absolute:
+      break;
+    case ARM::reloc_arm_branch: {
+      // relocation to b and bl instructions
+      ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
+      *((unsigned*)RelocPos) |= ResultPtr;
+      break;
+    }
+    }
+  }
 }
diff --git a/lib/Target/ARM/ARMRelocations.h b/lib/Target/ARM/ARMRelocations.h
index beea52b..7e33d97 100644
--- a/lib/Target/ARM/ARMRelocations.h
+++ b/lib/Target/ARM/ARMRelocations.h
@@ -19,7 +19,11 @@
 namespace llvm {
   namespace ARM {
     enum RelocationType {
+      reloc_arm_relative,
 
+      reloc_arm_absolute,
+
+      reloc_arm_branch
     };
   }
 }
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index b29f84d..d5f0ffa 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -37,7 +37,7 @@ namespace {
 /// ThumbTargetMachine - Create an Thumb architecture model.
 ///
 unsigned ThumbTargetMachine::getJITMatchQuality() {
-#if defined(__arm__)
+#if defined(__thumb__)
   return 10;
 #endif
   return 0;
@@ -87,7 +87,7 @@ ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS,
     TLInfo(*this) {}
 
 unsigned ARMTargetMachine::getJITMatchQuality() {
-#if defined(__thumb__)
+#if defined(__arm__)
   return 10;
 #endif
   return 0;