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author | Evan Cheng <evan.cheng@apple.com> | 2008-09-01 08:25:56 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-09-01 08:25:56 +0000 |
commit | 10a9eb8212f68cf86bb53471070bbb9cc2c2b422 (patch) | |
tree | afc031893d58739c4c2b3be781720d7d38332e46 | |
parent | d36b01cdc722ea8cd327995358a89a0f19802464 (diff) | |
download | external_llvm-10a9eb8212f68cf86bb53471070bbb9cc2c2b422.zip external_llvm-10a9eb8212f68cf86bb53471070bbb9cc2c2b422.tar.gz external_llvm-10a9eb8212f68cf86bb53471070bbb9cc2c2b422.tar.bz2 |
Control flow instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 78 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 10 |
2 files changed, 71 insertions, 17 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 16fb405..d60ba5f 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -135,10 +135,76 @@ class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm, list<dag> pattern> : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, "", pattern>; + +// Ctrl flow instructions +class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc, + string asm, list<dag> pattern> + : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, + asm,"",pattern> { + let Inst{24} = 1; // L bit + let Inst{25-27} = 5; +} +class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm, + list<dag> pattern> + : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, + "", pattern> { + let Inst{24} = 1; // L bit + let Inst{25-27} = 5; +} +class ABLXI<bits<4> opcod, dag oops, dag iops, Format f, string asm, + list<dag> pattern> + : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, + "", pattern> { + let Inst{4-7} = 3; + let Inst{20-27} = 0x12; +} +// FIXME: BX class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm, list<dag> pattern> : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm, "", pattern>; +class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm, + list<dag> pattern> + : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, + "", pattern> { + let Inst{24} = 0; // L bit + let Inst{25-27} = 5; +} +class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc, + string asm, list<dag> pattern> + : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, + asm,"",pattern> { + let Inst{24} = 0; // L bit + let Inst{25-27} = 5; +} + +// BR_JT instructions +// == mov pc +class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> + : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc, + asm, "", pattern> { + let Inst{20} = 0; // S Bit + let Inst{21-24} = 0xd; + let Inst{26-27} = 0; +} +// == ldr pc +class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> + : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc, + asm, "", pattern> { + let Inst{20} = 1; // L bit + let Inst{21} = 0; // W bit + let Inst{22} = 0; // B bit + let Inst{24} = 1; // P bit +} +// == add pc +class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> + : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc, + asm, "", pattern> { + let Inst{20} = 0; // S bit + let Inst{21-24} = 4; + let Inst{26-27} = 0; +} + // addrmode1 instructions class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, @@ -606,18 +672,6 @@ class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm, } -// BR_JT instructions -class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc, - asm, "", pattern>; -class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc, - asm, "", pattern>; -class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc, - asm, "", pattern>; - - //===----------------------------------------------------------------------===// // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index cfc0625..b4a9f42f 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -531,16 +531,16 @@ let isReturn = 1, isTerminator = 1 in let isCall = 1, Defs = [R0, R1, R2, R3, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { - def BL : AXI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch, + def BL : ABLI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch, "bl ${func:call}", [(ARMcall tglobaladdr:$func)]>; - def BL_pred : AI<0xB, (outs), (ins i32imm:$func, variable_ops), - Branch, "bl", " ${func:call}", + def BL_pred : ABLpredI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch, + "bl", " ${func:call}", [(ARMcall_pred tglobaladdr:$func)]>; // ARMv5T and above - def BLX : AXI<0x2, (outs), (ins GPR:$func, variable_ops), BranchMisc, + def BLX : ABLXI<0x2, (outs), (ins GPR:$func, variable_ops), BranchMisc, "blx $func", [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>; let Uses = [LR] in { @@ -576,7 +576,7 @@ let isBranch = 1, isTerminator = 1 in { // FIXME: should be able to write a pattern for ARMBrcond, but can't use // a two-value operand where a dag node expects two operands. :( - def Bcc : AI<0xA, (outs), (ins brtarget:$target), Branch, + def Bcc : ABccI<0xA, (outs), (ins brtarget:$target), Branch, "b", " $target", [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; } |