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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 13:56:11 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 13:56:11 +0000 |
| commit | 11275eba1747f82276a8f954c13f3ff4881e995b (patch) | |
| tree | 10146696c3bedde37d82cb0ed413d0488c03d2ec | |
| parent | 338cf05f16e3d0f1f0de1c0d8969f11bc7df1240 (diff) | |
| download | external_llvm-11275eba1747f82276a8f954c13f3ff4881e995b.zip external_llvm-11275eba1747f82276a8f954c13f3ff4881e995b.tar.gz external_llvm-11275eba1747f82276a8f954c13f3ff4881e995b.tar.bz2 | |
Fix thinko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75957 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/SystemZ/SystemZRegisterInfo.td | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td index bdff542..4030cfd 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -119,26 +119,24 @@ def F15 : FPR<15, "f15">, DwarfRegNum<[31]>; def PSW : SystemZReg<"psw">; def subreg_32bit : PatLeaf<(i32 1)>; -def subreg_64even : PatLeaf<(i32 2)>; -def subreg_64odd : PatLeaf<(i32 3)>; -def subreg_32even : PatLeaf<(i32 4)>; -def subreg_32odd : PatLeaf<(i32 5)>; +def subreg_even : PatLeaf<(i32 1)>; +def subreg_odd : PatLeaf<(i32 2)>; def : SubRegSet<1, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D], [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>; -def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], +def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>; -def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], +def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>; -def : SubRegSet<4, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], +def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>; -def : SubRegSet<5, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], +def : SubRegSet<2, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>; /// Register classes |