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| author | Richard Osborne <richard@xmos.com> | 2009-11-14 19:33:35 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2009-11-14 19:33:35 +0000 |
| commit | 13c4fabf99366fe9c3b6d7d3e4e7f7e0539624a8 (patch) | |
| tree | 655dc7119222080ae40e99f56403278be18babd4 | |
| parent | b23f3aa2701374ae54d6bd1732eb225217edc5a2 (diff) | |
| download | external_llvm-13c4fabf99366fe9c3b6d7d3e4e7f7e0539624a8.zip external_llvm-13c4fabf99366fe9c3b6d7d3e4e7f7e0539624a8.tar.gz external_llvm-13c4fabf99366fe9c3b6d7d3e4e7f7e0539624a8.tar.bz2 | |
Add XCore support for arbitrary-sized aggregate returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88802 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 11 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.h | 6 | ||||
| -rw-r--r-- | test/CodeGen/XCore/bigstructret.ll | 43 |
3 files changed, 60 insertions, 0 deletions
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 0e1e1ef..16e68fe 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -918,6 +918,17 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, // Return Value Calling Convention Implementation //===----------------------------------------------------------------------===// +bool XCoreTargetLowering:: +CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<EVT> &OutTys, + const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, + SelectionDAG &DAG) { + SmallVector<CCValAssign, 16> RVLocs; + CCState CCInfo(CallConv, isVarArg, getTargetMachine(), + RVLocs, *DAG.getContext()); + return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore); +} + SDValue XCoreTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h index ef8555e..10631af 100644 --- a/lib/Target/XCore/XCoreISelLowering.h +++ b/lib/Target/XCore/XCoreISelLowering.h @@ -159,6 +159,12 @@ namespace llvm { CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, DebugLoc dl, SelectionDAG &DAG); + + virtual bool + CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<EVT> &OutTys, + const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, + SelectionDAG &DAG); }; } diff --git a/test/CodeGen/XCore/bigstructret.ll b/test/CodeGen/XCore/bigstructret.ll new file mode 100644 index 0000000..56af930 --- /dev/null +++ b/test/CodeGen/XCore/bigstructret.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -march=xcore | FileCheck %s + +%0 = type { i32, i32, i32, i32 } +%1 = type { i32, i32, i32, i32, i32 } + +; Structs of 4 words can be returned in registers +define internal fastcc %0 @ReturnBigStruct() nounwind readnone { +entry: + %0 = insertvalue %0 zeroinitializer, i32 12, 0 + %1 = insertvalue %0 %0, i32 24, 1 + %2 = insertvalue %0 %1, i32 48, 2 + %3 = insertvalue %0 %2, i32 24601, 3 + ret %0 %3 +} +; CHECK: ReturnBigStruct: +; CHECK: ldc r0, 12 +; CHECK: ldc r1, 24 +; CHECK: ldc r2, 48 +; CHECK: ldc r3, 24601 +; CHECK: retsp 0 + +; Structs bigger than 4 words are returned via a hidden hidden sret-parameter +define internal fastcc %1 @ReturnBigStruct2() nounwind readnone { +entry: + %0 = insertvalue %1 zeroinitializer, i32 12, 0 + %1 = insertvalue %1 %0, i32 24, 1 + %2 = insertvalue %1 %1, i32 48, 2 + %3 = insertvalue %1 %2, i32 24601, 3 + %4 = insertvalue %1 %3, i32 4321, 4 + ret %1 %4 +} +; CHECK: ReturnBigStruct2: +; CHECK: ldc r1, 4321 +; CHECK: stw r1, r0[4] +; CHECK: ldc r1, 24601 +; CHECK: stw r1, r0[3] +; CHECK: ldc r1, 48 +; CHECK: stw r1, r0[2] +; CHECK: ldc r1, 24 +; CHECK: stw r1, r0[1] +; CHECK: ldc r1, 12 +; CHECK: stw r1, r0[0] +; CHECK: retsp 0 |