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| author | Chris Lattner <sabre@nondot.org> | 2005-09-09 20:51:08 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-09-09 20:51:08 +0000 |
| commit | 1463019e84cea6857914cea30c0180ec7289f09f (patch) | |
| tree | cfd20c8e831acb0a342c14495579d72c8238b158 | |
| parent | 50ea01ed5ba23c8988af9fed0b91178e69140a80 (diff) | |
| download | external_llvm-1463019e84cea6857914cea30c0180ec7289f09f.zip external_llvm-1463019e84cea6857914cea30c0180ec7289f09f.tar.gz external_llvm-1463019e84cea6857914cea30c0180ec7289f09f.tar.bz2 | |
code cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23297 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index a296d32..750d979 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -214,8 +214,9 @@ PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { // convert into indexed form of the instruction // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 - unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()]; - assert(NewOpcode && "No indexed form of load or store available!"); + assert(ImmToIdxMap.count(MI.getOpcode()) && + "No indexed form of load or store available!"); + unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; MI.setOpcode(NewOpcode); MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); MI.SetMachineOperandReg(2, PPC::R0); |