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| author | Bill Wendling <isanbard@gmail.com> | 2010-10-12 22:08:41 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-10-12 22:08:41 +0000 |
| commit | 174777bb2b0a1896afb5dc5ff96a91d162d00149 (patch) | |
| tree | 6de8374f31202f7868fd9995f7273e6fb255b8ee | |
| parent | a0c14ef8f6a41184c65a7904e70efa268ab241f9 (diff) | |
| download | external_llvm-174777bb2b0a1896afb5dc5ff96a91d162d00149.zip external_llvm-174777bb2b0a1896afb5dc5ff96a91d162d00149.tar.gz external_llvm-174777bb2b0a1896afb5dc5ff96a91d162d00149.tar.bz2 | |
Encoding for VADDD. Plus a test for the VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 17 | ||||
| -rw-r--r-- | test/MC/ARM/simple-fp-encoding.ll | 23 |
2 files changed, 37 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 1d29ff8..3fb8ebe 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -142,9 +142,20 @@ def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, // FP Binary Operations. // -def VADDD : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b), - IIC_fpALU64, "vadd", ".f64\t$dst, $a, $b", - [(set DPR:$dst, (fadd DPR:$a, (f64 DPR:$b)))]>; +def VADDD : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), + IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]> { + bits<5> Dd; + bits<5> Dn; + bits<5> Dm; + + let Inst{3-0} = Dm{3-0}; + let Inst{5} = Dm{4}; + let Inst{19-16} = Dn{3-0}; + let Inst{7} = Dn{4}; + let Inst{15-12} = Dd{3-0}; + let Inst{22} = Dd{4}; +} def VADDS : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", diff --git a/test/MC/ARM/simple-fp-encoding.ll b/test/MC/ARM/simple-fp-encoding.ll new file mode 100644 index 0000000..755ec07 --- /dev/null +++ b/test/MC/ARM/simple-fp-encoding.ll @@ -0,0 +1,23 @@ +;RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s + + +; FIXME: Once the ARM integrated assembler is up and going, these sorts of tests +; should run on .s source files rather than using llc to generate the +; assembly. + + +define arm_aapcscc float @f1(float %a, float %b) nounwind { +entry: +; CHECK: f1 +; CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee] + %add = fadd float %a, %b + ret float %add +} + +define arm_aapcscc double @f2(double %a, double %b) nounwind { +entry: +; CHECK: f2 +; CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] + %add = fadd double %a, %b + ret double %add +} |