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| author | Chris Lattner <sabre@nondot.org> | 2010-12-15 05:51:39 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-12-15 05:51:39 +0000 |
| commit | 1a0fbe2cf438ac2788df669284293789681424e1 (patch) | |
| tree | ea11bc8217c895545c74d3f9478ea7ce26315395 | |
| parent | ba3c8155704e5e2ac24b5069c32bca359b0738ed (diff) | |
| download | external_llvm-1a0fbe2cf438ac2788df669284293789681424e1.zip external_llvm-1a0fbe2cf438ac2788df669284293789681424e1.tar.gz external_llvm-1a0fbe2cf438ac2788df669284293789681424e1.tar.bz2 | |
when transforming a MULHS into a wider MUL, there is no need to SRA the
result, the top bits are truncated off anyway, just use SRL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 740b29b..6f0c167 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1940,7 +1940,7 @@ SDValue DAGCombiner::visitMULHS(SDNode *N) { N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); - N1 = DAG.getNode(ISD::SRA, DL, NewVT, N1, + N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, DAG.getConstant(SimpleSize, getShiftAmountTy())); return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); } |