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| author | Richard Relph <Richard.Relph@amd.com> | 2013-03-12 18:17:18 +0000 |
|---|---|---|
| committer | Richard Relph <Richard.Relph@amd.com> | 2013-03-12 18:17:18 +0000 |
| commit | 1a5c0510ecb029b7e5d04249cdd4e50b97bf1c3f (patch) | |
| tree | 708ae5849994dde477f714baedcadbc3c30259ac | |
| parent | 2ee69f1be6473bef40862f4c55e0b33d141c6380 (diff) | |
| download | external_llvm-1a5c0510ecb029b7e5d04249cdd4e50b97bf1c3f.zip external_llvm-1a5c0510ecb029b7e5d04249cdd4e50b97bf1c3f.tar.gz external_llvm-1a5c0510ecb029b7e5d04249cdd4e50b97bf1c3f.tar.bz2 | |
Avoid generating ISD::SELECT for vector operands to SIGN_EXTEND
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176881 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 716fb93..61603e1 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4496,8 +4496,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { NegOne, DAG.getConstant(0, VT), cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); if (SCC.getNode()) return SCC; - if (!LegalOperations || - TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) + if (!VT.isVector() && (!LegalOperations || + TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))) return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, DAG.getSetCC(N->getDebugLoc(), TLI.getSetCCResultType(VT), |