Rename "ADDO" to "SADDO" and "UADDO". The "UADDO" isn't equivalent to "ADDC"

because the boolean it returns to indicate an overflow may not be treated like
as a flag. It could be stored to memory, for instance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59780 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 22 insertions, 14 deletions

diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index b55cc8e..93d2b64 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -250,13 +250,14 @@ namespace ISD {
     // values.
     ADDE, SUBE,
 
-    // RESULT, OVERFLOW_FLAG, OUTCHAIN = ADDO(INCHAIN, LHS, RHS) -
-    // Overflow-aware node for arithmetic operations. This node takes two
-    // operands: the normal lhs and rhs to the add. It produces two results: the
-    // normal result of the add, and a flag indicating whether an overflow
-    // occured. This node is generated from the llvm.sadd.with.overflow
-    // intrinsic. It is lowered by target-dependent code.
-    ADDO,
+    // RESULT, BOOL, OUTCHAIN = [SU]ADDO(INCHAIN, LHS, RHS) - Overflow-aware
+    // node for arithmetic operations. This node takes two operands: the normal
+    // lhs and rhs to the add. It produces two results: the normal result of the
+    // add, and a boolean to indicate if an overflow occured (this isn't a flag,
+    // because it may be stored to memory, etc.). This node is generated from
+    // the llvm.sadd.with.overflow intrinsic. It is lowered by target-dependent
+    // code.
+    SADDO, UADDO,
 
     // Simple binary floating point operators.
     FADD, FSUB, FMUL, FDIV, FREM,
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index cbb6506..e2aad48 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -190,7 +190,8 @@ namespace {
     SDValue visitBUILD_VECTOR(SDNode *N);
     SDValue visitCONCAT_VECTORS(SDNode *N);
     SDValue visitVECTOR_SHUFFLE(SDNode *N);
-    SDValue visitADDO(SDNode *N);
+    SDValue visitSADDO(SDNode *N);
+    SDValue visitUADDO(SDNode *N);
 
     SDValue XformToShuffleWithZero(SDNode *N);
     SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS);
@@ -728,7 +729,8 @@ SDValue DAGCombiner::visit(SDNode *N) {
   case ISD::BUILD_VECTOR:       return visitBUILD_VECTOR(N);
   case ISD::CONCAT_VECTORS:     return visitCONCAT_VECTORS(N);
   case ISD::VECTOR_SHUFFLE:     return visitVECTOR_SHUFFLE(N);
-  case ISD::ADDO:               return visitADDO(N);
+  case ISD::SADDO:              return visitSADDO(N);
+  case ISD::UADDO:              return visitUADDO(N);
   }
   return SDValue();
 }
@@ -5145,7 +5147,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
   return SDValue();
 }
 
-SDValue DAGCombiner::visitADDO(SDNode *N) {
+SDValue DAGCombiner::visitSADDO(SDNode *N) {
   SDValue Chain = N->getOperand(2);
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
@@ -5173,6 +5175,10 @@ SDValue DAGCombiner::visitADDO(SDNode *N) {
   return SDValue(N, 0);
 }
 
+SDValue DAGCombiner::visitUADDO(SDNode *N) {
+  return SDValue();
+}
+
 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
 /// an AND to a vector_shuffle with the destination vector and a zero vector.
 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 189985f..d22a65d 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5151,7 +5151,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
   case ISD::CARRY_FALSE:         return "carry_false";
   case ISD::ADDC:        return "addc";
   case ISD::ADDE:        return "adde";
-  case ISD::ADDO:        return "addo";
+  case ISD::SADDO:       return "saddo";
+  case ISD::UADDO:       return "uaddo";
   case ISD::SUBC:        return "subc";
   case ISD::SUBE:        return "sube";
   case ISD::SHL_PARTS:   return "shl_parts";
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index da62b6d..75910ef 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -4094,7 +4094,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
   }
 
   case Intrinsic::sadd_with_overflow: {
-    // Convert to "ISD::ADDO" instruction.
+    // Convert to "ISD::SADDO" instruction.
     SDValue Chain = getRoot();
     SDValue Op1 = getValue(I.getOperand(1));
     SDValue Op2 = getValue(I.getOperand(2));
@@ -4103,7 +4103,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     MVT ValueVTs[] = { Ty, MVT::i1, MVT::Other };
     SDValue Ops[] = { Op1, Op2, Chain };
 
-    SDValue Result = DAG.getNode(ISD::ADDO, DAG.getVTList(&ValueVTs[0], 3),
+    SDValue Result = DAG.getNode(ISD::SADDO, DAG.getVTList(&ValueVTs[0], 3),
                                  &Ops[0], 3);
 
     setValue(&I, Result);
@@ -4113,7 +4113,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     return 0;
   }
   case Intrinsic::uadd_with_overflow: {
-    // TODO: Convert to "ISD::ADDC" instruction.
+    // TODO: Convert to "ISD::UADDO" instruction.
     return 0;
   }