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author | Akira Hatanaka <ahatanaka@mips.com> | 2013-09-06 23:40:15 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-09-06 23:40:15 +0000 |
commit | 1d04ca7987ef0abb5be07b11e3bb9c9e756a1fce (patch) | |
tree | d0dc569e06404a16064bc3447d814eaa64a8ebb5 | |
parent | 77e1ebd18fc558620b97fe38f3ebbf825533655f (diff) | |
download | external_llvm-1d04ca7987ef0abb5be07b11e3bb9c9e756a1fce.zip external_llvm-1d04ca7987ef0abb5be07b11e3bb9c9e756a1fce.tar.gz external_llvm-1d04ca7987ef0abb5be07b11e3bb9c9e756a1fce.tar.bz2 |
[mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
equivalent to "beq $zero, $zero, offset".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190220 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp | 5 | ||||
-rw-r--r-- | lib/Target/Mips/MipsCodeEmitter.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 11 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 9 |
4 files changed, 13 insertions, 16 deletions
diff --git a/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp b/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp index 755a948..231d485 100644 --- a/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ b/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -230,8 +230,11 @@ bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI, bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) { switch (MI.getOpcode()) { case Mips::BEQ: + // beq $zero, $zero, $L2 => b $L2 // beq $r0, $zero, $L2 => beqz $r0, $L2 - return isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); + return isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && + printAlias("b", MI, 2, OS) || + isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); case Mips::BEQ64: // beq $r0, $zero, $L2 => beqz $r0, $L2 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); diff --git a/lib/Target/Mips/MipsCodeEmitter.cpp b/lib/Target/Mips/MipsCodeEmitter.cpp index eed1155..0f1917a 100644 --- a/lib/Target/Mips/MipsCodeEmitter.cpp +++ b/lib/Target/Mips/MipsCodeEmitter.cpp @@ -323,6 +323,10 @@ bool MipsCodeEmitter::expandPseudos(MachineBasicBlock::instr_iterator &MI, BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO) .addReg(Mips::ZERO).addImm(0); break; + case Mips::B: + BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::BEQ)).addReg(Mips::ZERO) + .addReg(Mips::ZERO).addOperand(MI->getOperand(0)); + break; case Mips::JALRPseudo: BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::JALR), Mips::RA) .addReg(MI->getOperand(0).getReg()); diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index f87d70e..c536264 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -297,17 +297,6 @@ class BGEZ_FM<bits<6> op, bits<5> funct> { let Inst{15-0} = offset; } -class B_FM { - bits<16> offset; - - bits<32> Inst; - - let Inst{31-26} = 4; - let Inst{25-21} = 0; - let Inst{20-16} = 0; - let Inst{15-0} = offset; -} - class SLTI_FM<bits<6> op> : StdArch { bits<5> rt; bits<5> rs; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 8b985a8..83c7885 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -542,9 +542,9 @@ class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, } // Unconditional branch -class UncondBranch<string opstr> : - InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), - [(br bb:$offset)], IIBranch, FrmI> { +class UncondBranch<Instruction BEQInst> : + PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>, + PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { let isBranch = 1; let isTerminator = 1; let isBarrier = 1; @@ -966,13 +966,13 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>; def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, Requires<[RelocStatic, HasStdEnc]>, IsBranch; def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>; -def B : UncondBranch<"b">, B_FM; def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>; def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>; def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>; def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>; def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>; def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>; +def B : UncondBranch<BEQ>; def JAL : JumpLink<"jal">, FJ<3>; def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; @@ -1100,6 +1100,7 @@ def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; +def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; def : InstAlias<"bnez $rs,$offset", (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; def : InstAlias<"beqz $rs,$offset", |