Reapply r158846.

Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 249 insertions, 274 deletions

diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index 571a481..042b456 100644
--- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -13,16 +13,15 @@
 
 #include "Mips.h"
 #include "MipsSubtarget.h"
+#include "MipsRegisterInfo.h"
 #include "llvm/MC/EDInstInfo.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/Support/MemoryObject.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/MathExtras.h"
 
-
 #include "MipsGenEDInfo.inc"
 
 using namespace llvm;
@@ -31,123 +30,71 @@ typedef MCDisassembler::DecodeStatus DecodeStatus;
 
 namespace {
 
-/// MipsDisassembler - a disasembler class for Mips32.
-class MipsDisassembler : public MCDisassembler {
+/// MipsDisassemblerBase - a disasembler class for Mips.
+class MipsDisassemblerBase : public MCDisassembler {
 public:
   /// Constructor     - Initializes the disassembler.
   ///
-  MipsDisassembler(const MCSubtargetInfo &STI, bool bigEndian) :
-    MCDisassembler(STI), isBigEndian(bigEndian) {
-  }
+  MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
+                       bool bigEndian) :
+    MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {}
 
-  ~MipsDisassembler() {
-  }
-
-  /// getInstruction - See MCDisassembler.
-  DecodeStatus getInstruction(MCInst &instr,
-                              uint64_t &size,
-                              const MemoryObject &region,
-                              uint64_t address,
-                              raw_ostream &vStream,
-                              raw_ostream &cStream) const;
+  virtual ~MipsDisassemblerBase() {}
 
   /// getEDInfo - See MCDisassembler.
   const EDInstInfo *getEDInfo() const;
 
+  const MCRegisterInfo *getRegInfo() const { return RegInfo; }
+
 private:
+  const MCRegisterInfo *RegInfo;
+protected:
   bool isBigEndian;
 };
 
-
-/// Mips64Disassembler - a disasembler class for Mips64.
-class Mips64Disassembler : public MCDisassembler {
+/// MipsDisassembler - a disasembler class for Mips32.
+class MipsDisassembler : public MipsDisassemblerBase {
 public:
   /// Constructor     - Initializes the disassembler.
   ///
-  Mips64Disassembler(const MCSubtargetInfo &STI, bool bigEndian) :
-    MCDisassembler(STI), isBigEndian(bigEndian) {
-  }
-
-  ~Mips64Disassembler() {
-  }
+  MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
+                   bool bigEndian) :
+    MipsDisassemblerBase(STI, Info, bigEndian) {}
 
   /// getInstruction - See MCDisassembler.
-  DecodeStatus getInstruction(MCInst &instr,
-                              uint64_t &size,
-                              const MemoryObject &region,
-                              uint64_t address,
-                              raw_ostream &vStream,
-                              raw_ostream &cStream) const;
+  virtual DecodeStatus getInstruction(MCInst &instr,
+                                      uint64_t &size,
+                                      const MemoryObject &region,
+                                      uint64_t address,
+                                      raw_ostream &vStream,
+                                      raw_ostream &cStream) const;
+};
 
-  /// getEDInfo - See MCDisassembler.
-  const EDInstInfo *getEDInfo() const;
 
-private:
-  bool isBigEndian;
+/// Mips64Disassembler - a disasembler class for Mips64.
+class Mips64Disassembler : public MipsDisassemblerBase {
+public:
+  /// Constructor     - Initializes the disassembler.
+  ///
+  Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
+                     bool bigEndian) :
+    MipsDisassemblerBase(STI, Info, bigEndian) {}
+
+  /// getInstruction - See MCDisassembler.
+  virtual DecodeStatus getInstruction(MCInst &instr,
+                                      uint64_t &size,
+                                      const MemoryObject &region,
+                                      uint64_t address,
+                                      raw_ostream &vStream,
+                                      raw_ostream &cStream) const;
 };
 
 } // end anonymous namespace
 
-const EDInstInfo *MipsDisassembler::getEDInfo() const {
-  return instInfoMips;
-}
-
-const EDInstInfo *Mips64Disassembler::getEDInfo() const {
+const EDInstInfo *MipsDisassemblerBase::getEDInfo() const {
   return instInfoMips;
 }
 
-// Decoder tables for Mips register
-static const uint16_t CPURegsTable[] = {
-  Mips::ZERO, Mips::AT, Mips::V0, Mips::V1,
-  Mips::A0, Mips::A1, Mips::A2, Mips::A3,
-  Mips::T0, Mips::T1, Mips::T2, Mips::T3,
-  Mips::T4, Mips::T5, Mips::T6, Mips::T7,
-  Mips::S0, Mips::S1, Mips::S2, Mips::S3,
-  Mips::S4, Mips::S5, Mips::S6, Mips::S7,
-  Mips::T8, Mips::T9, Mips::K0, Mips::K1,
-  Mips::GP, Mips::SP, Mips::FP, Mips::RA
-};
-
-static const uint16_t FGR32RegsTable[] = {
-  Mips::F0, Mips::F1, Mips::F2, Mips::F3,
-  Mips::F4, Mips::F5, Mips::F6, Mips::F7,
-  Mips::F8, Mips::F9, Mips::F10, Mips::F11,
-  Mips::F12, Mips::F13, Mips::F14, Mips::F15,
-  Mips::F16, Mips::F17, Mips::F18, Mips::F18,
-  Mips::F20, Mips::F21, Mips::F22, Mips::F23,
-  Mips::F24, Mips::F25, Mips::F26, Mips::F27,
-  Mips::F28, Mips::F29, Mips::F30, Mips::F31
-};
-
-static const uint16_t CPU64RegsTable[] = {
-  Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64,
-  Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
-  Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64,
-  Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64,
-  Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64,
-  Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64,
-  Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64,
-  Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64
-};
-
-static const uint16_t FGR64RegsTable[] = {
-  Mips::D0_64,  Mips::D1_64,  Mips::D2_64,  Mips::D3_64,
-  Mips::D4_64,  Mips::D5_64,  Mips::D6_64,  Mips::D7_64,
-  Mips::D8_64,  Mips::D9_64,  Mips::D10_64, Mips::D11_64,
-  Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
-  Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64,
-  Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64,
-  Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64,
-  Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64
-};
-
-static const uint16_t AFGR64RegsTable[] = {
-  Mips::D0,  Mips::D1,  Mips::D2,  Mips::D3,
-  Mips::D4,  Mips::D5,  Mips::D6,  Mips::D7,
-  Mips::D8,  Mips::D9,  Mips::D10, Mips::D11,
-  Mips::D12, Mips::D13, Mips::D14, Mips::D15
-};
-
 // Forward declare these because the autogenerated code will reference them.
 // Definitions are further down.
 static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
@@ -243,25 +190,25 @@ extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 static MCDisassembler *createMipsDisassembler(
                        const Target &T,
                        const MCSubtargetInfo &STI) {
-  return new MipsDisassembler(STI,true);
+  return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
 }
 
 static MCDisassembler *createMipselDisassembler(
                        const Target &T,
                        const MCSubtargetInfo &STI) {
-  return new MipsDisassembler(STI,false);
+  return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
 }
 
 static MCDisassembler *createMips64Disassembler(
                        const Target &T,
                        const MCSubtargetInfo &STI) {
-  return new Mips64Disassembler(STI,true);
+  return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
 }
 
 static MCDisassembler *createMips64elDisassembler(
                        const Target &T,
                        const MCSubtargetInfo &STI) {
-  return new Mips64Disassembler(STI, false);
+  return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
 }
 
 extern "C" void LLVMInitializeMipsDisassembler() {
@@ -366,6 +313,11 @@ Mips64Disassembler::getInstruction(MCInst &instr,
   return MCDisassembler::Fail;
 }
 
+static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
+  const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
+  return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
+}
+
 static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
                                                  unsigned RegNo,
                                                  uint64_t Address,
@@ -374,7 +326,8 @@ static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
-  Inst.addOperand(MCOperand::CreateReg(CPU64RegsTable[RegNo]));
+  unsigned Reg = getReg(Decoder, Mips::CPU64RegsRegClassID, RegNo);
+  Inst.addOperand(MCOperand::CreateReg(Reg));
   return MCDisassembler::Success;
 }
 
@@ -384,8 +337,8 @@ static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
                                                const void *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
-
-  Inst.addOperand(MCOperand::CreateReg(CPURegsTable[RegNo]));
+  unsigned Reg = getReg(Decoder, Mips::CPURegsRegClassID, RegNo);
+  Inst.addOperand(MCOperand::CreateReg(Reg));
   return MCDisassembler::Success;
 }
 
@@ -396,7 +349,8 @@ static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
-  Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[RegNo]));
+  unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
+  Inst.addOperand(MCOperand::CreateReg(Reg));
   return MCDisassembler::Success;
 }
 
@@ -407,7 +361,8 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
-  Inst.addOperand(MCOperand::CreateReg(FGR32RegsTable[RegNo]));
+  unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
+  Inst.addOperand(MCOperand::CreateReg(Reg));
   return MCDisassembler::Success;
 }
 
@@ -424,15 +379,18 @@ static DecodeStatus DecodeMem(MCInst &Inst,
                               uint64_t Address,
                               const void *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
-  int Reg = (int)fieldFromInstruction32(Insn, 16, 5);
-  int Base = (int)fieldFromInstruction32(Insn, 21, 5);
+  unsigned Reg = fieldFromInstruction32(Insn, 16, 5);
+  unsigned Base = fieldFromInstruction32(Insn, 21, 5);
+
+  Reg = getReg(Decoder, Mips::CPURegsRegClassID, Reg);
+  Base = getReg(Decoder, Mips::CPURegsRegClassID, Base);
 
   if(Inst.getOpcode() == Mips::SC){
-    Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
+    Inst.addOperand(MCOperand::CreateReg(Reg));
   }
 
-  Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
-  Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
+  Inst.addOperand(MCOperand::CreateReg(Reg));
+  Inst.addOperand(MCOperand::CreateReg(Base));
   Inst.addOperand(MCOperand::CreateImm(Offset));
 
   return MCDisassembler::Success;
@@ -443,11 +401,14 @@ static DecodeStatus DecodeFMem(MCInst &Inst,
                                uint64_t Address,
                                const void *Decoder) {
   int Offset = SignExtend32<16>(Insn & 0xffff);
-  int Reg = (int)fieldFromInstruction32(Insn, 16, 5);
-  int Base = (int)fieldFromInstruction32(Insn, 21, 5);
+  unsigned Reg = fieldFromInstruction32(Insn, 16, 5);
+  unsigned Base = fieldFromInstruction32(Insn, 21, 5);
 
-  Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[Reg]));
-  Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
+  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
+  Base = getReg(Decoder, Mips::CPURegsRegClassID, Base);
+
+  Inst.addOperand(MCOperand::CreateReg(Reg));
+  Inst.addOperand(MCOperand::CreateReg(Base));
   Inst.addOperand(MCOperand::CreateImm(Offset));
 
   return MCDisassembler::Success;
@@ -478,10 +439,12 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
                                               unsigned RegNo,
                                               uint64_t Address,
                                               const void *Decoder) {
-  if (RegNo > 31)
+  if (RegNo > 30 || RegNo %2)
     return MCDisassembler::Fail;
 
-  Inst.addOperand(MCOperand::CreateReg(AFGR64RegsTable[RegNo]));
+  ;
+  unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
+  Inst.addOperand(MCOperand::CreateReg(Reg));
   return MCDisassembler::Success;
 }
 
@@ -492,7 +455,7 @@ static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
   //Currently only hardware register 29 is supported
   if (RegNo != 29)
     return  MCDisassembler::Fail;
-  Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
+  Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));
   return MCDisassembler::Success;
 }
 
diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt
index 591d8c4..25a8d9a 100644
--- a/test/MC/Disassembler/Mips/mips32.txt
+++ b/test/MC/Disassembler/Mips/mips32.txt
@@ -1,7 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux
 
 # CHECK: abs.d $f12,$f14
-0x46 0x20 0x39 0x85
+0x46 0x20 0x73 0x05
 
 # CHECK: abs.s $f6,$f7
 0x46 0x00 0x39 0x85
@@ -9,8 +9,8 @@
 # CHECK: add t1,a2,a3
 0x00 0xc7 0x48 0x20
 
-# CHECK: add.d $f18,$f12,$f14
-0x46 0x27 0x32 0x40
+# CHECK: add.d $f8,$f12,$f14
+0x46 0x2e 0x62 0x00
 
 # CHECK: add.s $f9,$f6,$f7
 0x46 0x07 0x32 0x40
@@ -61,103 +61,103 @@
 0x15 0x26 0x01 0x4c
 
 # CHECK: c.eq.d $f12,$f14
-0x46 0x27 0x30 0x32
+0x46 0x2e 0x60 0x32
 
 # CHECK: c.eq.s $f6,$f7
 0x46 0x07 0x30 0x32
 
 # CHECK: c.f.d $f12,$f14
-0x46 0x27 0x30 0x30
+0x46 0x2e 0x60 0x30
 
 # CHECK: c.f.s $f6,$f7
 0x46 0x07 0x30 0x30
 
 # CHECK: c.le.d $f12,$f14
-0x46 0x27 0x30 0x3e
+0x46 0x2e 0x60 0x3e
 
 # CHECK: c.le.s $f6,$f7
 0x46 0x07 0x30 0x3e
 
 # CHECK: c.lt.d $f12,$f14
-0x46 0x27 0x30 0x3c
+0x46 0x2e 0x60 0x3c
 
 # CHECK: c.lt.s $f6,$f7
 0x46 0x07 0x30 0x3c
 
 # CHECK: c.nge.d $f12,$f14
-0x46 0x27 0x30 0x3d
+0x46 0x2e 0x60 0x3d
 
 # CHECK: c.nge.s $f6,$f7
 0x46 0x07 0x30 0x3d
 
 # CHECK: c.ngl.d $f12,$f14
-0x46 0x27 0x30 0x3b
+0x46 0x2e 0x60 0x3b
 
 # CHECK: c.ngl.s $f6,$f7
 0x46 0x07 0x30 0x3b
 
 # CHECK: c.ngle.d $f12,$f14
-0x46 0x27 0x30 0x39
+0x46 0x2e 0x60 0x39
 
 # CHECK: c.ngle.s $f6,$f7
 0x46 0x07 0x30 0x39
 
 # CHECK: c.ngt.d $f12,$f14
-0x46 0x27 0x30 0x3f
+0x46 0x2e 0x60 0x3f
 
 # CHECK: c.ngt.s $f6,$f7
 0x46 0x07 0x30 0x3f
 
 # CHECK: c.ole.d $f12,$f14
-0x46 0x27 0x30 0x36
+0x46 0x2e 0x60 0x36
 
 # CHECK: c.ole.s $f6,$f7
 0x46 0x07 0x30 0x36
 
 # CHECK: c.olt.d $f12,$f14
-0x46 0x27 0x30 0x34
+0x46 0x2e 0x60 0x34
 
 # CHECK: c.olt.s $f6,$f7
 0x46 0x07 0x30 0x34
 
 # CHECK: c.seq.d $f12,$f14
-0x46 0x27 0x30 0x3a
+0x46 0x2e 0x60 0x3a
 
 # CHECK: c.seq.s $f6,$f7
 0x46 0x07 0x30 0x3a
 
 # CHECK: c.sf.d $f12,$f14
-0x46 0x27 0x30 0x38
+0x46 0x2e 0x60 0x38
 
 # CHECK: c.sf.s $f6,$f7
 0x46 0x07 0x30 0x38
 
 # CHECK: c.ueq.d $f12,$f14
-0x46 0x27 0x30 0x33
+0x46 0x2e 0x60 0x33
 
 # CHECK: c.ueq.s $f28,$f18
 0x46 0x12 0xe0 0x33
 
 # CHECK: c.ule.d $f12,$f14
-0x46 0x27 0x30 0x37
+0x46 0x2e 0x60 0x37
 
 # CHECK: c.ule.s $f6,$f7
 0x46 0x07 0x30 0x37
 
 # CHECK: c.ult.d $f12,$f14
-0x46 0x27 0x30 0x35
+0x46 0x2e 0x60 0x35
 
 # CHECK: c.ult.s $f6,$f7
 0x46 0x07 0x30 0x35
 
 # CHECK: c.un.d $f12,$f14
-0x46 0x27 0x30 0x31
+0x46 0x2e 0x60 0x31
 
 # CHECK: c.un.s $f6,$f7
 0x46 0x07 0x30 0x31
 
 # CHECK: ceil.w.d $f12,$f14
-0x46 0x20 0x39 0x8e
+0x46 0x20 0x73 0x0e
 
 # CHECK: ceil.w.s $f6,$f7
 0x46 0x00 0x39 0x8e
@@ -175,31 +175,25 @@
 0x44 0xc6 0x38 0x00
 
 # CHECK: cvt.d.s $f6,$f7
-0x46 0x00 0x38 0xa1
+0x46 0x00 0x39 0xa1
 
 # CHECK: cvt.d.w $f12,$f14
-0x46 0x80 0x38 0xa1
-
-# CHECK: cvt.l.d $f12,$f14
-0x46 0x20 0x39 0xa5
-
-# CHECK: cvt.l.s $f6,$f7
-0x46 0x00 0x39 0xa5
+0x46 0x80 0x73 0x21
 
 # CHECK: cvt.s.d $f12,$f14
-0x46 0x20 0x39 0xa0
+0x46 0x20 0x73 0x20
 
 # CHECK: cvt.s.w $f6,$f7
 0x46 0x80 0x39 0xa0
 
 # CHECK: cvt.w.d $f12,$f14
-0x46 0x20 0x39 0xa4
+0x46 0x20 0x73 0x24
 
 # CHECK: cvt.w.s $f6,$f7
 0x46 0x00 0x39 0xa4
 
 # CHECK: floor.w.d $f12,$f14
-0x46 0x20 0x39 0x8f
+0x46 0x20 0x73 0x0f
 
 # CHECK: floor.w.s $f6,$f7
 0x46 0x00 0x39 0x8f
@@ -246,6 +240,12 @@
 # CHECK: lwc1  $f9,9158(a3)
 0xc4 0xe9 0x23 0xc6
 
+# CHECK: lwl   $v0, 3($a0)
+0x88 0x82 0x00 0x03
+
+# CHECK: lwr   $v1,16($a1)
+0x98 0xa3 0x00 0x10
+
 # CHECK: madd  a2,a3
 0x70 0xc7 0x00 0x00
 
@@ -261,8 +261,8 @@
 # CHECK: mflo  a1
 0x00 0x00 0x28 0x12
 
-# CHECK: mov.d $f6,$f7
-0x46 0x20 0x39 0x86
+# CHECK: mov.d $f6,$f8
+0x46 0x20 0x41 0x86
 
 # CHECK: mov.s $f6,$f7
 0x46 0x00 0x39 0x86
@@ -285,8 +285,8 @@
 # CHECK: mtlo  a3
 0x00 0xe0 0x00 0x13
 
-# CHECK: mul.d $f9,$f12,$f14
-0x46 0x27 0x32 0x42
+# CHECK: mul.d $f8,$f12,$f14
+0x46 0x2e 0x62 0x02
 
 # CHECK: mul.s $f9,$f6,$f7
 0x46 0x07 0x32 0x42
@@ -301,7 +301,7 @@
 0x00 0x65 0x00 0x19
 
 # CHECK: neg.d $f12,$f14
-0x46 0x20 0x39 0x87
+0x46 0x20 0x73 0x07
 
 # CHECK: neg.s $f6,$f7
 0x46 0x00 0x39 0x87
@@ -327,8 +327,8 @@
 # CHECK: rdhwr a2,$29
 0x7c 0x06 0xe8 0x3b
 
-# CHECK: round.w.d $f12,$f14
-0x46 0x20 0x39 0x8c
+# CHECK: round.w.d $f6,$f14
+0x46 0x20 0x73 0x0c
 
 # CHECK: round.w.s $f6,$f7
 0x46 0x00 0x39 0x8c
@@ -367,7 +367,7 @@
 0x00 0x65 0x18 0x2b
 
 # CHECK: sqrt.d  $f12,$f14
-0x46 0x20 0x39 0x84
+0x46 0x20 0x73 0x04
 
 # CHECK: sqrt.s  $f6,$f7
 0x46 0x00 0x39 0x84
@@ -387,8 +387,8 @@
 # CHECK: srlv  v0,v1,a1
 0x00 0xa3 0x10 0x06
 
-# CHECK: sub.d $f9,$f12,$f14
-0x46 0x27 0x32 0x41
+# CHECK: sub.d $f8,$f12,$f14
+0x46 0x2e 0x62 0x01
 
 # CHECK: sub.s $f9,$f6,$f7
 0x46 0x07 0x32 0x41
@@ -405,11 +405,17 @@
 # CHECK: swc1  $f9,9158(a3)
 0xe4 0xe9 0x23 0xc6
 
+# CHECK: swl $a0, 16($a1)
+0xa8 0xa4 0x00 0x10
+
+# CHECK: swr $a2, 16($a3)
+0xb8 0xe6 0x00 0x10
+
 # CHECK: sync  0x7
 0x00 0x00 0x01 0xcf
 
 # CHECK: trunc.w.d $f12,$f14
-0x46 0x20 0x39 0x8d
+0x46 0x20 0x73 0x0d
 
 # CHECK: trunc.w.s $f6,$f7
 0x46 0x00 0x39 0x8d
diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt
index a5a3cfd..020e787 100644
--- a/test/MC/Disassembler/Mips/mips32_le.txt
+++ b/test/MC/Disassembler/Mips/mips32_le.txt
@@ -1,7 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux
 
 # CHECK: abs.d $f12,$f14
-0x85 0x39 0x20 0x46
+0x05 0x73 0x20 0x46
 
 # CHECK: abs.s $f6,$f7
 0x85 0x39 0x00 0x46
@@ -9,8 +9,8 @@
 # CHECK: add t1,a2,a3
 0x20 0x48 0xc7 0x00
 
-# CHECK: add.d $f18,$f12,$f14
-0x40 0x32 0x27 0x46
+# CHECK: add.d $8,$f12,$f14
+0x00 0x62 0x2e 0x46
 
 # CHECK: add.s $f9,$f6,$f7
 0x40 0x32 0x07 0x46
@@ -61,106 +61,106 @@
 0x4c 0x01 0x26 0x15
 
 # CHECK: c.eq.d $f12,$f14
-0x32 0x30 0x27 0x46
+0x32 0x60 0x2e 0x46
 
 # CHECK: c.eq.s $f6,$f7
 0x32 0x30 0x07 0x46
 
 # CHECK: c.f.d $f12,$f14
-0x30 0x30 0x27 0x46
+0x30 0x60 0x2e 0x46
 
 # CHECK: c.f.s $f6,$f7
 0x30 0x30 0x07 0x46
 
 # CHECK: c.le.d $f12,$f14
-0x3e 0x30 0x27 0x46
+0x3e 0x60 0x2e 0x46
 
 # CHECK: c.le.s $f6,$f7
 0x3e 0x30 0x07 0x46
 
 # CHECK: c.lt.d $f12,$f14
-0x3c 0x30 0x27 0x46
+0x3c 0x60 0x2e 0x46
 
 # CHECK: c.lt.s $f6,$f7
 0x3c 0x30 0x07 0x46
 
 # CHECK: c.nge.d $f12,$f14
-0x3d 0x30 0x27 0x46
+0x3d 0x60 0x2e 0x46
 
 # CHECK: c.nge.s $f6,$f7
 0x3d 0x30 0x07 0x46
 
 # CHECK: c.ngl.d $f12,$f14
-0x3b 0x30 0x27 0x46
+0x3b 0x60 0x2e 0x46
 
 # CHECK: c.ngl.s $f6,$f7
 0x3b 0x30 0x07 0x46
 
 # CHECK: c.ngle.d $f12,$f14
-0x39 0x30 0x27 0x46
+0x39 0x60 0x2e 0x46
 
 # CHECK: c.ngle.s $f6,$f7
 0x39 0x30 0x07 0x46
 
 # CHECK: c.ngt.d $f12,$f14
-0x3f 0x30 0x27 0x46
+0x3f 0x60 0x2e 0x46
 
 # CHECK: c.ngt.s $f6,$f7
 0x3f 0x30 0x07 0x46
 
 # CHECK: c.ole.d $f12,$f14
-0x36 0x30 0x27 0x46
+0x36 0x60 0x2e 0x46
 
 # CHECK: c.ole.s $f6,$f7
 0x36 0x30 0x07 0x46
 
 # CHECK: c.olt.d $f12,$f14
-0x34 0x30 0x27 0x46
+0x34 0x60 0x2e 0x46
 
 # CHECK: c.olt.s $f6,$f7
 0x34 0x30 0x07 0x46
 
 # CHECK: c.seq.d $f12,$f14
-0x3a 0x30 0x27 0x46
+0x3a 0x60 0x2e 0x46
 
 # CHECK: c.seq.s $f6,$f7
 0x3a 0x30 0x07 0x46
 
 # CHECK: c.sf.d $f12,$f14
-0x38 0x30 0x27 0x46
+0x38 0x60 0x2e 0x46
 
 # CHECK: c.sf.s $f6,$f7
 0x38 0x30 0x07 0x46
 
 # CHECK: c.ueq.d $f12,$f14
-0x33 0x30 0x27 0x46
+0x33 0x60 0x2e 0x46
 
 # CHECK: c.ueq.s $f28,$f18
 0x33 0xe0 0x12 0x46
 
 # CHECK: c.ule.d $f12,$f14
-0x37 0x30 0x27 0x46
+0x37 0x60 0x2e 0x46
 
 # CHECK: c.ule.s $f6,$f7
 0x37 0x30 0x07 0x46
 
 # CHECK: c.ult.d $f12,$f14
-0x35 0x30 0x27 0x46
+0x35 0x60 0x2e 0x46
 
 # CHECK: c.ult.s $f6,$f7
 0x35 0x30 0x07 0x46
 
 # CHECK: c.un.d $f12,$f14
-0x31 0x30 0x27 0x46
+0x31 0x60 0x2e 0x46
 
 # CHECK: c.un.s $f6,$f7
 0x31 0x30 0x07 0x46
 
 # CHECK: ceil.w.d $f12,$f14
-0x8e 0x38 0x20 0x46
+0x0e 0x73 0x20 0x46
 
 # CHECK: ceil.w.s $f6,$f7
-0x8e 0x38 0x00 0x46
+0x0e 0x73 0x20 0x46
 
 # CHECK: cfc1 a2,$7
 0x00 0x38 0x46 0x44
@@ -178,28 +178,22 @@
 0xa1 0x39 0x00 0x46
 
 # CHECK: cvt.d.w $f12,$f14
-0xa1 0x39 0x80 0x46
-
-# CHECK: cvt.l.d $f12,$f14
-0xa5 0x39 0x20 0x46
-
-# CHECK: cvt.l.s $f6,$f7
-0xa5 0x39 0x00 0x46
+0x21 0x73 0x80 0x46
 
 # CHECK: cvt.s.d $f12,$f14
-0xa0 0x39 0x20 0x46
+0x20 0x73 0x20 0x46
 
 # CHECK: cvt.s.w $f6,$f7
 0xa0 0x39 0x80 0x46
 
 # CHECK: cvt.w.d $f12,$f14
-0xa4 0x39 0x20 0x46
+0x24 0x73 0x20 0x46
 
 # CHECK: cvt.w.s $f6,$f7
 0xa4 0x39 0x00 0x46
 
 # CHECK: floor.w.d $f12,$f14
-0x8f 0x39 0x20 0x46
+0x0f 0x73 0x20 0x46
 
 # CHECK: floor.w.s $f6,$f7
 0x8f 0x39 0x00 0x46
@@ -210,7 +204,7 @@
 # CHECK: jal 00000530
 0x4c 0x01 0x00 0x0c
 
-# CHECK: jalr a2,a3
+# CHECK: jalr a3
 0x09 0xf8 0xe0 0x00
 
 # CHECK: jr a3
@@ -249,6 +243,12 @@
 # CHECK: lwc1  $f9,9158(a3)
 0xc6 0x23 0xe9 0xc4
 
+# CHECK: lwl   $v0, 3($a0)
+0x03 0x00 0x82 0x88
+
+# CHECK: lwr   $v1,16($a1)
+0x10 0x00 0xa3 0x98
+
 # CHECK: madd  a2,a3
 0x00 0x00 0xc7 0x70
 
@@ -264,8 +264,8 @@
 # CHECK: mflo  a1
 0x12 0x28 0x00 0x00
 
-# CHECK: mov.d $f12,$f14
-0x86 0x39 0x20 0x46
+# CHECK: mov.d $f6,$f8
+0x86 0x41 0x20 0x46
 
 # CHECK: mov.s $f6,$f7
 0x86 0x39 0x00 0x46
@@ -288,11 +288,11 @@
 # CHECK: mtlo  a3
 0x13 0x00 0xe0 0x00
 
-# CHECK: mul.d $f9,$f12,$f14
-0x42 0x32 0x27 0x46
+# CHECK: mul.d $f8,$f12,$f14
+0x02 0x62 0x2e 0x46
 
 # CHECK: mul.s $f9,$f6,$f7
-0x42 0x32 0x07 0x46
+0x02 0x62 0x07 0x46
 
 # CHECK: mul t1,a2,a3
 0x02 0x48 0xc7 0x70
@@ -304,7 +304,7 @@
 0x19 0x00 0x65 0x00
 
 # CHECK: neg.d $f12,$f14
-0x87 0x39 0x20 0x46
+0x07 0x73 0x20 0x46
 
 # CHECK: neg.s $f6,$f7
 0x87 0x39 0x00 0x46
@@ -331,7 +331,7 @@
 0x3b 0xe8 0x06 0x7c
 
 # CHECK: round.w.d $f12,$f14
-0x8c 0x39 0x20 0x46
+0x0c 0x73 0x20 0x46
 
 # CHECK: round.w.s $f6,$f7
 0x8c 0x39 0x00 0x46
@@ -370,7 +370,7 @@
 0x2b 0x18 0x65 0x00
 
 # CHECK: sqrt.d  $f12,$f14
-0x84 0x39 0x20 0x46
+0x04 0x73 0x20 0x46
 
 # CHECK: sqrt.s  $f6,$f7
 0x84 0x39 0x00 0x46
@@ -390,8 +390,8 @@
 # CHECK: srlv  v0,v1,a1
 0x06 0x10 0xa3 0x00
 
-# CHECK: sub.d $f9,$f12,$f14
-0x41 0x32 0x27 0x46
+# CHECK: sub.d $f8,$f12,$f14
+0x01 0x62 0x2e 0x46
 
 # CHECK: sub.s $f9,$f6,$f7
 0x41 0x32 0x07 0x46
@@ -408,11 +408,17 @@
 # CHECK: swc1  $f9,9158(a3)
 0xc6 0x23 0xe9 0xe4
 
+# CHECK: swl $a0, 16($a1)
+0x10 0x00 0xa4 0xa8
+
+# CHECK: swr $a2, 16($a3)
+0x10 0x00 0xe6 0xb8
+
 # CHECK: sync  0x7
 0xcf 0x01 0x00 0x00
 
 # CHECK: trunc.w.d $f12,$f14
-0x8d 0x39 0x20 0x46
+0x0d 0x73 0x20 0x46
 
 # CHECK: trunc.w.s $f6,$f7
 0x8d 0x39 0x00 0x46
diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt
index 295ffd0..3bf2493 100644
--- a/test/MC/Disassembler/Mips/mips32r2.txt
+++ b/test/MC/Disassembler/Mips/mips32r2.txt
@@ -1,7 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2
 
 # CHECK: abs.d $f12,$f14
-0x46 0x20 0x39 0x85
+0x46 0x20 0x73 0x05
 
 # CHECK: abs.s $f6,$f7
 0x46 0x00 0x39 0x85
@@ -9,8 +9,8 @@
 # CHECK: add t1,a2,a3
 0x00 0xc7 0x48 0x20
 
-# CHECK: add.d $f18,$f12,$f14
-0x46 0x27 0x32 0x40
+# CHECK: add.d $f8,$f12,$f14
+0x46 0x2e 0x62 0x00
 
 # CHECK: add.s $f9,$f6,$f7
 0x46 0x07 0x32 0x40
@@ -61,103 +61,103 @@
 0x15 0x26 0x01 0x4c
 
 # CHECK: c.eq.d $f12,$f14
-0x46 0x27 0x30 0x32
+0x46 0x2e 0x60 0x32
 
 # CHECK: c.eq.s $f6,$f7
 0x46 0x07 0x30 0x32
 
 # CHECK: c.f.d $f12,$f14
-0x46 0x27 0x30 0x30
+0x46 0x2e 0x60 0x30
 
 # CHECK: c.f.s $f6,$f7
 0x46 0x07 0x30 0x30
 
 # CHECK: c.le.d $f12,$f14
-0x46 0x27 0x30 0x3e
+0x46 0x2e 0x60 0x3e
 
 # CHECK: c.le.s $f6,$f7
 0x46 0x07 0x30 0x3e
 
 # CHECK: c.lt.d $f12,$f14
-0x46 0x27 0x30 0x3c
+0x46 0x2e 0x60 0x3c
 
 # CHECK: c.lt.s $f6,$f7
 0x46 0x07 0x30 0x3c
 
 # CHECK: c.nge.d $f12,$f14
-0x46 0x27 0x30 0x3d
+0x46 0x2e 0x60 0x3d
 
 # CHECK: c.nge.s $f6,$f7
 0x46 0x07 0x30 0x3d
 
 # CHECK: c.ngl.d $f12,$f14
-0x46 0x27 0x30 0x3b
+0x46 0x2e 0x60 0x3b
 
 # CHECK: c.ngl.s $f6,$f7
 0x46 0x07 0x30 0x3b
 
 # CHECK: c.ngle.d $f12,$f14
-0x46 0x27 0x30 0x39
+0x46 0x2e 0x60 0x39
 
 # CHECK: c.ngle.s $f6,$f7
 0x46 0x07 0x30 0x39
 
 # CHECK: c.ngt.d $f12,$f14
-0x46 0x27 0x30 0x3f
+0x46 0x2e 0x60 0x3f
 
 # CHECK: c.ngt.s $f6,$f7
 0x46 0x07 0x30 0x3f
 
 # CHECK: c.ole.d $f12,$f14
-0x46 0x27 0x30 0x36
+0x46 0x2e 0x60 0x36
 
 # CHECK: c.ole.s $f6,$f7
 0x46 0x07 0x30 0x36
 
 # CHECK: c.olt.d $f12,$f14
-0x46 0x27 0x30 0x34
+0x46 0x2e 0x60 0x34
 
 # CHECK: c.olt.s $f6,$f7
 0x46 0x07 0x30 0x34
 
 # CHECK: c.seq.d $f12,$f14
-0x46 0x27 0x30 0x3a
+0x46 0x2e 0x60 0x3a
 
 # CHECK: c.seq.s $f6,$f7
 0x46 0x07 0x30 0x3a
 
 # CHECK: c.sf.d $f12,$f14
-0x46 0x27 0x30 0x38
+0x46 0x2e 0x60 0x38
 
 # CHECK: c.sf.s $f6,$f7
 0x46 0x07 0x30 0x38
 
 # CHECK: c.ueq.d $f12,$f14
-0x46 0x27 0x30 0x33
+0x46 0x2e 0x60 0x33
 
 # CHECK: c.ueq.s $f28,$f18
 0x46 0x12 0xe0 0x33
 
 # CHECK: c.ule.d $f12,$f14
-0x46 0x27 0x30 0x37
+0x46 0x2e 0x60 0x37
 
 # CHECK: c.ule.s $f6,$f7
 0x46 0x07 0x30 0x37
 
 # CHECK: c.ult.d $f12,$f14
-0x46 0x27 0x30 0x35
+0x46 0x2e 0x60 0x35
 
 # CHECK: c.ult.s $f6,$f7
 0x46 0x07 0x30 0x35
 
 # CHECK: c.un.d $f12,$f14
-0x46 0x27 0x30 0x31
+0x46 0x2e 0x60 0x31
 
 # CHECK: c.un.s $f6,$f7
 0x46 0x07 0x30 0x31
 
 # CHECK: ceil.w.d $f12,$f14
-0x46 0x20 0x39 0x8e
+0x46 0x20 0x73 0x0e
 
 # CHECK: ceil.w.s $f6,$f7
 0x46 0x00 0x39 0x8e
@@ -175,31 +175,31 @@
 0x44 0xc6 0x38 0x00
 
 # CHECK: cvt.d.s $f6,$f7
-0x46 0x00 0x38 0xa1
+0x46 0x00 0x39 0xa1
 
 # CHECK: cvt.d.w $f12,$f14
-0x46 0x80 0x38 0xa1
+0x46 0x80 0x73 0x21
 
 # CHECK: cvt.l.d $f12,$f14
-0x46 0x20 0x39 0xa5
+0x46 0x20 0x73 0x05
 
 # CHECK: cvt.l.s $f6,$f7
 0x46 0x00 0x39 0xa5
 
 # CHECK: cvt.s.d $f12,$f14
-0x46 0x20 0x39 0xa0
+0x46 0x20 0x73 0x20
 
 # CHECK: cvt.s.w $f6,$f7
 0x46 0x80 0x39 0xa0
 
 # CHECK: cvt.w.d $f12,$f14
-0x46 0x20 0x39 0xa4
+0x46 0x20 0x73 0x24
 
 # CHECK: cvt.w.s $f6,$f7
 0x46 0x00 0x39 0xa4
 
 # CHECK: floor.w.d $f12,$f14
-0x46 0x20 0x39 0x8f
+0x46 0x20 0x73 0x0f
 
 # CHECK: floor.w.s $f6,$f7
 0x46 0x00 0x39 0x8f
@@ -264,8 +264,8 @@
 # CHECK: mflo  a1
 0x00 0x00 0x28 0x12
 
-# CHECK: mov.d $f6,$f7
-0x46 0x20 0x39 0x86
+# CHECK: mov.d $f6,$f8
+0x46 0x20 0x41 0x86
 
 # CHECK: mov.s $f6,$f7
 0x46 0x00 0x39 0x86
@@ -288,8 +288,8 @@
 # CHECK: mtlo  a3
 0x00 0xe0 0x00 0x13
 
-# CHECK: mul.d $f9,$f12,$f14
-0x46 0x27 0x32 0x42
+# CHECK: mul.d $f8,$f12,$f14
+0x46 0x2e 0x62 0x02
 
 # CHECK: mul.s $f9,$f6,$f7
 0x46 0x07 0x32 0x42
@@ -304,7 +304,7 @@
 0x00 0x65 0x00 0x19
 
 # CHECK: neg.d $f12,$f14
-0x46 0x20 0x39 0x87
+0x46 0x20 0x73 0x07
 
 # CHECK: neg.s $f6,$f7
 0x46 0x00 0x39 0x87
@@ -336,8 +336,8 @@
 # CHECK: rorv  t1,a2,a3
 0x00 0xe6 0x48 0x46
 
-# CHECK: round.w.d $f12,$f14
-0x46 0x20 0x39 0x8c
+# CHECK: round.w.d $f6,$f14
+0x46 0x20 0x73 0x0c
 
 # CHECK: round.w.s $f6,$f7
 0x46 0x00 0x39 0x8c
@@ -382,7 +382,7 @@
 0x00 0x65 0x18 0x2b
 
 # CHECK: sqrt.d  $f12,$f14
-0x46 0x20 0x39 0x84
+0x46 0x20 0x73 0x04
 
 # CHECK: sqrt.s  $f6,$f7
 0x46 0x00 0x39 0x84
@@ -402,8 +402,8 @@
 # CHECK: srlv  v0,v1,a1
 0x00 0xa3 0x10 0x06
 
-# CHECK: sub.d $f9,$f12,$f14
-0x46 0x27 0x32 0x41
+# CHECK: sub.d $f8,$f12,$f14
+0x46 0x2e 0x62 0x01
 
 # CHECK: sub.s $f9,$f6,$f7
 0x46 0x07 0x32 0x41
@@ -424,7 +424,7 @@
 0x00 0x00 0x01 0xcf
 
 # CHECK: trunc.w.d $f12,$f14
-0x46 0x20 0x39 0x8d
+0x46 0x20 0x73 0x0d
 
 # CHECK: trunc.w.s $f6,$f7
 0x46 0x00 0x39 0x8d
diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt
index 6d8be79..84eb3e0 100644
--- a/test/MC/Disassembler/Mips/mips32r2_le.txt
+++ b/test/MC/Disassembler/Mips/mips32r2_le.txt
@@ -1,7 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2
 
 # CHECK: abs.d $f12,$f14
-0x85 0x39 0x20 0x46
+0x05 0x73 0x20 0x46
 
 # CHECK: abs.s $f6,$f7
 0x85 0x39 0x00 0x46
@@ -9,8 +9,8 @@
 # CHECK: add t1,a2,a3
 0x20 0x48 0xc7 0x00
 
-# CHECK: add.d $f18,$f12,$f14
-0x40 0x32 0x27 0x46
+# CHECK: add.d $8,$f12,$f14
+0x00 0x62 0x2e 0x46
 
 # CHECK: add.s $f9,$f6,$f7
 0x40 0x32 0x07 0x46
@@ -61,106 +61,106 @@
 0x4c 0x01 0x26 0x15
 
 # CHECK: c.eq.d $f12,$f14
-0x32 0x30 0x27 0x46
+0x32 0x60 0x2e 0x46
 
 # CHECK: c.eq.s $f6,$f7
 0x32 0x30 0x07 0x46
 
 # CHECK: c.f.d $f12,$f14
-0x30 0x30 0x27 0x46
+0x30 0x60 0x2e 0x46
 
 # CHECK: c.f.s $f6,$f7
 0x30 0x30 0x07 0x46
 
 # CHECK: c.le.d $f12,$f14
-0x3e 0x30 0x27 0x46
+0x3e 0x60 0x2e 0x46
 
 # CHECK: c.le.s $f6,$f7
 0x3e 0x30 0x07 0x46
 
 # CHECK: c.lt.d $f12,$f14
-0x3c 0x30 0x27 0x46
+0x3c 0x60 0x2e 0x46
 
 # CHECK: c.lt.s $f6,$f7
 0x3c 0x30 0x07 0x46
 
 # CHECK: c.nge.d $f12,$f14
-0x3d 0x30 0x27 0x46
+0x3d 0x60 0x2e 0x46
 
 # CHECK: c.nge.s $f6,$f7
 0x3d 0x30 0x07 0x46
 
 # CHECK: c.ngl.d $f12,$f14
-0x3b 0x30 0x27 0x46
+0x3b 0x60 0x2e 0x46
 
 # CHECK: c.ngl.s $f6,$f7
 0x3b 0x30 0x07 0x46
 
 # CHECK: c.ngle.d $f12,$f14
-0x39 0x30 0x27 0x46
+0x39 0x60 0x2e 0x46
 
 # CHECK: c.ngle.s $f6,$f7
 0x39 0x30 0x07 0x46
 
 # CHECK: c.ngt.d $f12,$f14
-0x3f 0x30 0x27 0x46
+0x3f 0x60 0x2e 0x46
 
 # CHECK: c.ngt.s $f6,$f7
 0x3f 0x30 0x07 0x46
 
 # CHECK: c.ole.d $f12,$f14
-0x36 0x30 0x27 0x46
+0x36 0x60 0x2e 0x46
 
 # CHECK: c.ole.s $f6,$f7
 0x36 0x30 0x07 0x46
 
 # CHECK: c.olt.d $f12,$f14
-0x34 0x30 0x27 0x46
+0x34 0x60 0x2e 0x46
 
 # CHECK: c.olt.s $f6,$f7
 0x34 0x30 0x07 0x46
 
 # CHECK: c.seq.d $f12,$f14
-0x3a 0x30 0x27 0x46
+0x3a 0x60 0x2e 0x46
 
 # CHECK: c.seq.s $f6,$f7
 0x3a 0x30 0x07 0x46
 
 # CHECK: c.sf.d $f12,$f14
-0x38 0x30 0x27 0x46
+0x38 0x60 0x2e 0x46
 
 # CHECK: c.sf.s $f6,$f7
 0x38 0x30 0x07 0x46
 
 # CHECK: c.ueq.d $f12,$f14
-0x33 0x30 0x27 0x46
+0x33 0x60 0x2e 0x46
 
 # CHECK: c.ueq.s $f28,$f18
 0x33 0xe0 0x12 0x46
 
 # CHECK: c.ule.d $f12,$f14
-0x37 0x30 0x27 0x46
+0x37 0x60 0x2e 0x46
 
 # CHECK: c.ule.s $f6,$f7
 0x37 0x30 0x07 0x46
 
 # CHECK: c.ult.d $f12,$f14
-0x35 0x30 0x27 0x46
+0x35 0x60 0x2e 0x46
 
 # CHECK: c.ult.s $f6,$f7
 0x35 0x30 0x07 0x46
 
 # CHECK: c.un.d $f12,$f14
-0x31 0x30 0x27 0x46
+0x31 0x60 0x2e 0x46
 
 # CHECK: c.un.s $f6,$f7
 0x31 0x30 0x07 0x46
 
 # CHECK: ceil.w.d $f12,$f14
-0x8e 0x38 0x20 0x46
+0x0e 0x73 0x20 0x46
 
 # CHECK: ceil.w.s $f6,$f7
-0x8e 0x38 0x00 0x46
+0x0e 0x73 0x20 0x46
 
 # CHECK: cfc1 a2,$7
 0x00 0x38 0x46 0x44
@@ -178,28 +178,28 @@
 0xa1 0x39 0x00 0x46
 
 # CHECK: cvt.d.w $f12,$f14
-0xa1 0x39 0x80 0x46
+0x21 0x73 0x80 0x46
 
 # CHECK: cvt.l.d $f12,$f14
-0xa5 0x39 0x20 0x46
+0x05 0x73 0x20 0x46
 
 # CHECK: cvt.l.s $f6,$f7
 0xa5 0x39 0x00 0x46
 
 # CHECK: cvt.s.d $f12,$f14
-0xa0 0x39 0x20 0x46
+0x20 0x73 0x20 0x46
 
 # CHECK: cvt.s.w $f6,$f7
 0xa0 0x39 0x80 0x46
 
 # CHECK: cvt.w.d $f12,$f14
-0xa4 0x39 0x20 0x46
+0x24 0x73 0x20 0x46
 
 # CHECK: cvt.w.s $f6,$f7
 0xa4 0x39 0x00 0x46
 
 # CHECK: floor.w.d $f12,$f14
-0x8f 0x39 0x20 0x46
+0x0f 0x73 0x20 0x46
 
 # CHECK: floor.w.s $f6,$f7
 0x8f 0x39 0x00 0x46
@@ -213,7 +213,7 @@
 # CHECK: jal 00000530
 0x4c 0x01 0x00 0x0c
 
-# CHECK: jalr a2,a3
+# CHECK: jalr a3
 0x09 0xf8 0xe0 0x00
 
 # CHECK: jr a3
@@ -267,8 +267,8 @@
 # CHECK: mflo  a1
 0x12 0x28 0x00 0x00
 
-# CHECK: mov.d $f12,$f14
-0x86 0x39 0x20 0x46
+# CHECK: mov.d $f6,$f8
+0x86 0x41 0x20 0x46
 
 # CHECK: mov.s $f6,$f7
 0x86 0x39 0x00 0x46
@@ -291,11 +291,11 @@
 # CHECK: mtlo  a3
 0x13 0x00 0xe0 0x00
 
-# CHECK: mul.d $f9,$f12,$f14
-0x42 0x32 0x27 0x46
+# CHECK: mul.d $f8,$f12,$f14
+0x02 0x62 0x2e 0x46
 
 # CHECK: mul.s $f9,$f6,$f7
-0x42 0x32 0x07 0x46
+0x02 0x62 0x07 0x46
 
 # CHECK: mul t1,a2,a3
 0x02 0x48 0xc7 0x70
@@ -307,7 +307,7 @@
 0x19 0x00 0x65 0x00
 
 # CHECK: neg.d $f12,$f14
-0x87 0x39 0x20 0x46
+0x07 0x73 0x20 0x46
 
 # CHECK: neg.s $f6,$f7
 0x87 0x39 0x00 0x46
@@ -340,7 +340,7 @@
 0x46 0x48 0xe6 0x00
 
 # CHECK: round.w.d $f12,$f14
-0x8c 0x39 0x20 0x46
+0x0c 0x73 0x20 0x46
 
 # CHECK: round.w.s $f6,$f7
 0x8c 0x39 0x00 0x46
@@ -385,7 +385,7 @@
 0x2b 0x18 0x65 0x00
 
 # CHECK: sqrt.d  $f12,$f14
-0x84 0x39 0x20 0x46
+0x04 0x73 0x20 0x46
 
 # CHECK: sqrt.s  $f6,$f7
 0x84 0x39 0x00 0x46
@@ -405,8 +405,8 @@
 # CHECK: srlv  v0,v1,a1
 0x06 0x10 0xa3 0x00
 
-# CHECK: sub.d $f9,$f12,$f14
-0x41 0x32 0x27 0x46
+# CHECK: sub.d $f8,$f12,$f14
+0x01 0x62 0x2e 0x46
 
 # CHECK: sub.s $f9,$f6,$f7
 0x41 0x32 0x07 0x46
@@ -427,7 +427,7 @@
 0xcf 0x01 0x00 0x00
 
 # CHECK: trunc.w.d $f12,$f14
-0x8d 0x39 0x20 0x46
+0x0d 0x73 0x20 0x46
 
 # CHECK: trunc.w.s $f6,$f7
 0x8d 0x39 0x00 0x46