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authorAnton Korobeynikov <asl@math.spbu.ru>2009-08-21 15:41:56 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2009-08-21 15:41:56 +0000
commit25f1aa04ff27ddc3de9154ee58e64a96849ff66c (patch)
tree38c851eae04f0ac74711847332e3f4f8b0945b84
parent4678c2d4382cbac40b51c8d26080f92ee9a2e22f (diff)
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Fix a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79634 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86ISelDAGToDAG.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index b020e43..eb6048d 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -737,7 +737,7 @@ bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
// Under X86-64 non-small code model, GV (and friends) are 64-bits, so
// they cannot be folded into immediate fields.
// FIXME: This can be improved for kernel and other models?
- (M == CodeModel::Small || CodeModel::Kernel) &&
+ (M == CodeModel::Small || M == CodeModel::Kernel) &&
// Base and index reg must be 0 in order to use %rip as base and lowering
// must allow RIP.
!AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {