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author | Johnny Chen <johnny.chen@apple.com> | 2011-03-15 22:27:33 +0000 |
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committer | Johnny Chen <johnny.chen@apple.com> | 2011-03-15 22:27:33 +0000 |
commit | 276f6f9cf978fa7074687eead10a6db96c5afa6d (patch) | |
tree | 29e1ab7ba0cbb6d72ec8490f0e3d4483b5ab94ce | |
parent | 6046cffbaf584b5d6bd7baf827794a5f91a07a9b (diff) | |
download | external_llvm-276f6f9cf978fa7074687eead10a6db96c5afa6d.zip external_llvm-276f6f9cf978fa7074687eead10a6db96c5afa6d.tar.gz external_llvm-276f6f9cf978fa7074687eead10a6db96c5afa6d.tar.bz2 |
There were two issues fixed:
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 17 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 8 |
2 files changed, 12 insertions, 13 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 0211581..f0ef2ff 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -679,8 +679,8 @@ static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn, } // Branch Instructions. -// BLr9: SignExtend(Imm24:'00', 32) -// Bcc, BLr9_pred: SignExtend(Imm24:'00', 32) Pred0 Pred1 +// BL: SignExtend(Imm24:'00', 32) +// Bcc, BL_pred: SignExtend(Imm24:'00', 32) Pred0 Pred1 // SMC: ZeroExtend(imm4, 32) // SVC: ZeroExtend(Imm24, 32) // @@ -760,7 +760,7 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn, return true; } - assert((Opcode == ARM::Bcc || Opcode == ARM::BLr9 || Opcode == ARM::BLr9_pred + assert((Opcode == ARM::Bcc || Opcode == ARM::BL || Opcode == ARM::BL_pred || Opcode == ARM::SMC || Opcode == ARM::SVC) && "Unexpected Opcode"); @@ -778,12 +778,6 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned Imm26 = slice(insn, 23, 0) << 2; //Imm32 = signextend<signed int, 26>(Imm26); Imm32 = SignExtend32<26>(Imm26); - - // When executing an ARM instruction, PC reads as the address of the current - // instruction plus 8. The assembler subtracts 8 from the difference - // between the branch instruction and the target address, disassembler has - // to add 8 to compensate. - Imm32 += 8; } MI.addOperand(MCOperand::CreateImm(Imm32)); @@ -793,7 +787,7 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn, } // Misc. Branch Instructions. -// BLXr9, BXr9 +// BLX, BX // BX, BX_RET static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { @@ -810,8 +804,7 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, return true; // BLX and BX take one GPR reg. - if (Opcode == ARM::BLXr9 || Opcode == ARM::BLXr9_pred || - Opcode == ARM::BLX || Opcode == ARM::BLX_pred || + if (Opcode == ARM::BLX || Opcode == ARM::BLX_pred || Opcode == ARM::BX) { assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && "Reg operand expected"); diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 22a73f2..8b3b7c9 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,7 +1,13 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s # CHECK: b #0 -0xfe 0xff 0xff 0xea +0x00 0x00 0x00 0xea + +# CHECK: bl #7732 +0x8d 0x07 0x00 0xeb + +# CHECK: bleq #-4 +0xff 0xff 0xff 0x0b # CHECK: bfc r8, #0, #16 0x1f 0x80 0xcf 0xe7 |