diff options
author | Reed Kotler <rkotler@mips.com> | 2012-10-23 01:35:48 +0000 |
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committer | Reed Kotler <rkotler@mips.com> | 2012-10-23 01:35:48 +0000 |
commit | 293e5d0e0a4abce2c79a6bde338325ca1df0edab (patch) | |
tree | e936dfe3496659c5fe5ae59c21937b89c256a2cf | |
parent | 8245a17a14e44df02c4488563d3ab50bee91c349 (diff) | |
download | external_llvm-293e5d0e0a4abce2c79a6bde338325ca1df0edab.zip external_llvm-293e5d0e0a4abce2c79a6bde338325ca1df0edab.tar.gz external_llvm-293e5d0e0a4abce2c79a6bde338325ca1df0edab.tar.bz2 |
implement setXX patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166459 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 185 | ||||
-rw-r--r-- | test/CodeGen/Mips/seteq.ll | 21 | ||||
-rw-r--r-- | test/CodeGen/Mips/seteqz.ll | 24 | ||||
-rw-r--r-- | test/CodeGen/Mips/setge.ll | 27 | ||||
-rw-r--r-- | test/CodeGen/Mips/setgek.ll | 18 | ||||
-rw-r--r-- | test/CodeGen/Mips/setle.ll | 26 | ||||
-rw-r--r-- | test/CodeGen/Mips/setlt.ll | 21 | ||||
-rw-r--r-- | test/CodeGen/Mips/setltk.ll | 20 | ||||
-rw-r--r-- | test/CodeGen/Mips/setne.ll | 20 | ||||
-rw-r--r-- | test/CodeGen/Mips/setuge.ll | 26 | ||||
-rw-r--r-- | test/CodeGen/Mips/setugt.ll | 21 | ||||
-rw-r--r-- | test/CodeGen/Mips/setule.ll | 26 | ||||
-rw-r--r-- | test/CodeGen/Mips/setult.ll | 21 | ||||
-rw-r--r-- | test/CodeGen/Mips/setultk.ll | 20 |
14 files changed, 472 insertions, 4 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 2694b09..043b974 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -21,6 +21,19 @@ def mem16 : Operand<i32> { } // +// Compare a register and immediate and place result in CC +// Implicit use of T8 +// +// EXT-CCRR Instruction format +// +class FEXT_CCRXI16_ins<bits<5> _op, string asmstr, + InstrItinClass itin>: + FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), + !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> { + let isCodeGenOnly=1; +} + +// // EXT-I instruction format // class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : @@ -44,6 +57,17 @@ class FEXT_I816_ins<bits<3> _func, string asmstr, // Assembler formats in alphabetical order. // Natural and pseudos are mixed together. // +// Compare two registers and place result in CC +// Implicit use of T8 +// +// CC-RR Instruction format +// +class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : + FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), + !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> { + let isCodeGenOnly=1; +} + // // EXT-RI instruction format // @@ -562,7 +586,36 @@ def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; // def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; +// +// Format: SLTI rx, immediate MIPS16e +// Purpose: Set on Less Than Immediate (Extended) +// To record the result of a less-than comparison with a constant. +// +def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>; + +// +// Format: SLTIU rx, immediate MIPS16e +// Purpose: Set on Less Than Immediate Unsigned (Extended) +// To record the result of a less-than comparison with a constant. +// +def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>; + +// +// Format: SLT rx, ry MIPS16e +// Purpose: Set on Less Than +// To record the result of a less-than comparison. +// +def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>; + +def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>; + +// Format: SLTU rx, ry MIPS16e +// Purpose: Set on Less Than Unsigned +// To record the result of an unsigned less-than comparison. +// + +def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>; // // Format: SRAV ry, rx MIPS16e // Purpose: Shift Word Right Arithmetic Variable @@ -705,6 +758,17 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; +// setcc patterns + +class SetCC_R16<PatFrag cond_op, Instruction I>: + Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), + (I CPU16Regs:$rx, CPU16Regs:$ry)>; + +class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: + Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), + (I CPU16Regs:$rx, imm_type:$imm16)>; + + // // Some branch conditional patterns are not generated by llvm at this time. // Some are for seemingly arbitrary reasons not used: i.e. with signed number @@ -757,10 +821,10 @@ def: Mips16Pat // // never called because compiler transforms a >= k to a > (k-1) -//def: Mips16Pat -// <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), -// (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) -// >; +def: Mips16Pat + <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), + (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) + >; // // bcond-setlt @@ -859,5 +923,118 @@ def: Mips16Pat (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; +// +// When writing C code to test setxx these patterns, +// some will be transformed into +// other things. So we test using C code but using -O3 and -O0 +// +// seteq +// +def : Mips16Pat + <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), + (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; + +def : Mips16Pat + <(seteq CPU16Regs:$lhs, 0), + (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; + + +// +// setge +// + +def: Mips16Pat + <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), + (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), + (LiRxImmX16 1))>; + +// +// For constants, llvm transforms this to: +// x > (k -1) and then reverses the operands to use setlt. So this pattern +// is not used now by the compiler. (Presumably checking that k-1 does not +// overflow). The compiler never uses this at a the current time, due to +// other optimizations. +// +//def: Mips16Pat +// <(setge CPU16Regs:$lhs, immSExt16:$rhs), +// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), +// (LiRxImmX16 1))>; + +// This catches the x >= -32768 case by transforming it to x > -32769 +// +def: Mips16Pat + <(setgt CPU16Regs:$lhs, -32769), + (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), + (LiRxImmX16 1))>; + +// +// setgt +// +// + +def: Mips16Pat + <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), + (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; + +// +// setle +// +def: Mips16Pat + <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), + (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; + +// +// setlt +// +def: SetCC_R16<setlt, SltCCRxRy16>; + +def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; + +// +// setne +// +def : Mips16Pat + <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), + (SltuCCRxRy16 (LiRxImmX16 0), + (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; + + +// +// setuge +// +def: Mips16Pat + <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), + (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), + (LiRxImmX16 1))>; + +// this pattern will never be used because the compiler will transform +// x >= k to x > (k - 1) and then use SLT +// +//def: Mips16Pat +// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), +// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), +// (LiRxImmX16 1))>; + +// +// setugt +// +def: Mips16Pat + <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), + (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; + +// +// setule +// +def: Mips16Pat + <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), + (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; + +// +// setult +// +def: SetCC_R16<setult, SltuCCRxRy16>; + +def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; + def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; diff --git a/test/CodeGen/Mips/seteq.ll b/test/CodeGen/Mips/seteq.ll new file mode 100644 index 0000000..da840c8 --- /dev/null +++ b/test/CodeGen/Mips/seteq.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 1, align 4 +@j = global i32 10, align 4 +@k = global i32 1, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @i, align 4 + %1 = load i32* @k, align 4 + %cmp = icmp eq i32 %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}} +; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1 +; 16: move ${{[0-9]+}}, $t8 + ret void +} + diff --git a/test/CodeGen/Mips/seteqz.ll b/test/CodeGen/Mips/seteqz.ll new file mode 100644 index 0000000..d445be6 --- /dev/null +++ b/test/CodeGen/Mips/seteqz.ll @@ -0,0 +1,24 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 0, align 4 +@j = global i32 99, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @i, align 4 + %cmp = icmp eq i32 %0, 0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: sltiu ${{[0-9]+}}, 1 +; 16: move ${{[0-9]+}}, $t8 + %1 = load i32* @j, align 4 + %cmp1 = icmp eq i32 %1, 99 + %conv2 = zext i1 %cmp1 to i32 + store i32 %conv2, i32* @r2, align 4 +; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}} +; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1 +; 16: move ${{[0-9]+}}, $t8 + ret void +} diff --git a/test/CodeGen/Mips/setge.ll b/test/CodeGen/Mips/setge.ll new file mode 100644 index 0000000..94b499b --- /dev/null +++ b/test/CodeGen/Mips/setge.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@j = global i32 -5, align 4 +@k = global i32 10, align 4 +@l = global i32 20, align 4 +@m = global i32 10, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 +@r3 = common global i32 0, align 4 +@.str = private unnamed_addr constant [22 x i8] c"1 = %i\0A1 = %i\0A0 = %i\0A\00", align 1 + +define void @test() nounwind { +entry: + %0 = load i32* @k, align 4 + %1 = load i32* @j, align 4 + %cmp = icmp sge i32 %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: xor $[[REGISTER]], ${{[0-9]+}} + %2 = load i32* @m, align 4 + %cmp1 = icmp sge i32 %0, %2 + %conv2 = zext i1 %cmp1 to i32 + store i32 %conv2, i32* @r2, align 4 + ret void +} diff --git a/test/CodeGen/Mips/setgek.ll b/test/CodeGen/Mips/setgek.ll new file mode 100644 index 0000000..40aaa7c --- /dev/null +++ b/test/CodeGen/Mips/setgek.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@k = global i32 10, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 +@r3 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @k, align 4 + %cmp = icmp sgt i32 %0, -32769 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: slti ${{[0-9]+}}, -32768 +; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: xor ${{[0-9]+}}, $[[REGISTER]] + ret void +} diff --git a/test/CodeGen/Mips/setle.ll b/test/CodeGen/Mips/setle.ll new file mode 100644 index 0000000..f36fb43 --- /dev/null +++ b/test/CodeGen/Mips/setle.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@j = global i32 -5, align 4 +@k = global i32 10, align 4 +@l = global i32 20, align 4 +@m = global i32 10, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 +@r3 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @j, align 4 + %1 = load i32* @k, align 4 + %cmp = icmp sle i32 %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: xor $[[REGISTER]], ${{[0-9]+}} + %2 = load i32* @m, align 4 + %cmp1 = icmp sle i32 %2, %1 + %conv2 = zext i1 %cmp1 to i32 + store i32 %conv2, i32* @r2, align 4 + ret void +} diff --git a/test/CodeGen/Mips/setlt.ll b/test/CodeGen/Mips/setlt.ll new file mode 100644 index 0000000..435be8e --- /dev/null +++ b/test/CodeGen/Mips/setlt.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@j = global i32 -5, align 4 +@k = global i32 10, align 4 +@l = global i32 20, align 4 +@m = global i32 10, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 +@r3 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @j, align 4 + %1 = load i32* @k, align 4 + %cmp = icmp slt i32 %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: move ${{[0-9]+}}, $t8 + ret void +} diff --git a/test/CodeGen/Mips/setltk.ll b/test/CodeGen/Mips/setltk.ll new file mode 100644 index 0000000..c0b610e --- /dev/null +++ b/test/CodeGen/Mips/setltk.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@j = global i32 -5, align 4 +@k = global i32 10, align 4 +@l = global i32 20, align 4 +@m = global i32 10, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 +@r3 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @j, align 4 + %cmp = icmp slt i32 %0, 10 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: slti $[[REGISTER:[0-9]+]], 10 +; 16: move $[[REGISTER]], $t8 + ret void +} diff --git a/test/CodeGen/Mips/setne.ll b/test/CodeGen/Mips/setne.ll new file mode 100644 index 0000000..6460c83 --- /dev/null +++ b/test/CodeGen/Mips/setne.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 1, align 4 +@j = global i32 10, align 4 +@k = global i32 1, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @i, align 4 + %1 = load i32* @k, align 4 + %cmp = icmp ne i32 %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}} +; 16: sltu ${{[0-9]+}}, $[[REGISTER]] +; 16: move ${{[0-9]+}}, $t8 + ret void +} diff --git a/test/CodeGen/Mips/setuge.ll b/test/CodeGen/Mips/setuge.ll new file mode 100644 index 0000000..ac72b66 --- /dev/null +++ b/test/CodeGen/Mips/setuge.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@j = global i32 5, align 4 +@k = global i32 10, align 4 +@l = global i32 20, align 4 +@m = global i32 10, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 +@r3 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @k, align 4 + %1 = load i32* @j, align 4 + %cmp = icmp uge i32 %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} +; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: xor $[[REGISTER]], ${{[0-9]+}} + %2 = load i32* @m, align 4 + %cmp1 = icmp uge i32 %0, %2 + %conv2 = zext i1 %cmp1 to i32 + store i32 %conv2, i32* @r2, align 4 + ret void +} diff --git a/test/CodeGen/Mips/setugt.ll b/test/CodeGen/Mips/setugt.ll new file mode 100644 index 0000000..328f0e3 --- /dev/null +++ b/test/CodeGen/Mips/setugt.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@j = global i32 5, align 4 +@k = global i32 10, align 4 +@l = global i32 20, align 4 +@m = global i32 10, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 +@r3 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @k, align 4 + %1 = load i32* @j, align 4 + %cmp = icmp ugt i32 %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} +; 16: move ${{[0-9]+}}, $t8 + ret void +} diff --git a/test/CodeGen/Mips/setule.ll b/test/CodeGen/Mips/setule.ll new file mode 100644 index 0000000..792f2ae --- /dev/null +++ b/test/CodeGen/Mips/setule.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@j = global i32 5, align 4 +@k = global i32 10, align 4 +@l = global i32 20, align 4 +@m = global i32 10, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 +@r3 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @j, align 4 + %1 = load i32* @k, align 4 + %cmp = icmp ule i32 %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} +; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: xor $[[REGISTER]], ${{[0-9]+}} + %2 = load i32* @m, align 4 + %cmp1 = icmp ule i32 %2, %1 + %conv2 = zext i1 %cmp1 to i32 + store i32 %conv2, i32* @r2, align 4 + ret void +} diff --git a/test/CodeGen/Mips/setult.ll b/test/CodeGen/Mips/setult.ll new file mode 100644 index 0000000..56d2e8d --- /dev/null +++ b/test/CodeGen/Mips/setult.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@j = global i32 5, align 4 +@k = global i32 10, align 4 +@l = global i32 20, align 4 +@m = global i32 10, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 +@r3 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @j, align 4 + %1 = load i32* @k, align 4 + %cmp = icmp ult i32 %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} +; 16: move ${{[0-9]+}}, $t8 + ret void +} diff --git a/test/CodeGen/Mips/setultk.ll b/test/CodeGen/Mips/setultk.ll new file mode 100644 index 0000000..75b270e --- /dev/null +++ b/test/CodeGen/Mips/setultk.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@j = global i32 5, align 4 +@k = global i32 10, align 4 +@l = global i32 20, align 4 +@m = global i32 10, align 4 +@r1 = common global i32 0, align 4 +@r2 = common global i32 0, align 4 +@r3 = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @j, align 4 + %cmp = icmp ult i32 %0, 10 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @r1, align 4 +; 16: sltiu $[[REGISTER:[0-9]+]], 10 +; 16: move $[[REGISTER]], $t8 + ret void +} |