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| author | Jim Grosbach <grosbach@apple.com> | 2010-11-19 22:14:31 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-11-19 22:14:31 +0000 |
| commit | 2aeb6121a19aca7c317619f7ec37d7a770e9f03b (patch) | |
| tree | bd53e2ae944bf8f87809b827ca4452488065f9c8 | |
| parent | a1b4175b8e2d8f95498a8148586734c4e44f342b (diff) | |
| download | external_llvm-2aeb6121a19aca7c317619f7ec37d7a770e9f03b.zip external_llvm-2aeb6121a19aca7c317619f7ec37d7a770e9f03b.tar.gz external_llvm-2aeb6121a19aca7c317619f7ec37d7a770e9f03b.tar.bz2 | |
Add ARM encoding information for STRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119852 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 17 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 4 |
2 files changed, 4 insertions, 17 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 977c5e5..5d963d7 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -510,7 +510,7 @@ class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, } // stores -class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin, +class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list<dag> pattern> : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, opc, asm, "", pattern> { @@ -525,22 +525,9 @@ class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin, let Inst{19-16} = addr{12-9}; // Rn let Inst{15-12} = Rt; // Rt let Inst{11-8} = addr{7-4}; // imm7_4/zero - let Inst{7-4} = 0b1011; + let Inst{7-4} = op; let Inst{3-0} = addr{3-0}; // imm3_0/Rm } -class AI3std<dag oops, dag iops, Format f, InstrItinClass itin, - string opc, string asm, list<dag> pattern> - : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, - opc, asm, "", pattern> { - let Inst{4} = 1; - let Inst{5} = 1; // H bit - let Inst{6} = 1; // S bit - let Inst{7} = 1; - let Inst{20} = 0; // L bit - let Inst{21} = 0; // W bit - let Inst{24} = 1; // P bit - let Inst{27-25} = 0b000; -} // Pre-indexed stores class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 336c2c6..02db6ab 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1692,14 +1692,14 @@ def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb), // Store // Stores with truncate -def STRH : AI3sth<(outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, +def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, IIC_iStore_bh_r, "strh", "\t$Rt, $addr", [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; // Store doubleword let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, isCodeGenOnly = 1 in // $src2 doesn't exist in asm string -def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr), +def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr), StMiscFrm, IIC_iStore_d_r, "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>; |