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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-05 22:22:07 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-05 22:22:07 +0000 |
| commit | 2b272a1c8cb6d9f02223a598495d84cd9d75b13d (patch) | |
| tree | e1ccff0f0df8aabb36cc91f99045274af0bdeb4b | |
| parent | 425b76c2314ff7ee7ad507011bdda1988ae481ef (diff) | |
| download | external_llvm-2b272a1c8cb6d9f02223a598495d84cd9d75b13d.zip external_llvm-2b272a1c8cb6d9f02223a598495d84cd9d75b13d.tar.gz external_llvm-2b272a1c8cb6d9f02223a598495d84cd9d75b13d.tar.bz2 | |
R600: Implement TargetLowering::getVectorIdxTy()
We use MVT::i32 for the vector index type, because we use 32-bit
operations to caculate offsets when dynamically indexing vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187749 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.cpp | 9 | ||||
| -rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.h | 2 | ||||
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 8 |
3 files changed, 14 insertions, 5 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index 5db36b0..efd2756 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -121,6 +121,15 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : } } +//===----------------------------------------------------------------------===// +// Target Information +//===----------------------------------------------------------------------===// + +MVT AMDGPUTargetLowering::getVectorIdxTy() const { + return MVT::i32; +} + + //===---------------------------------------------------------------------===// // Target Properties //===---------------------------------------------------------------------===// diff --git a/lib/Target/R600/AMDGPUISelLowering.h b/lib/Target/R600/AMDGPUISelLowering.h index 0e1c131..f614e23 100644 --- a/lib/Target/R600/AMDGPUISelLowering.h +++ b/lib/Target/R600/AMDGPUISelLowering.h @@ -51,7 +51,7 @@ public: virtual bool isFAbsFree(EVT VT) const; virtual bool isFNegFree(EVT VT) const; - + virtual MVT getVectorIdxTy() const; virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 7ae0ffd..500d15e 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1792,25 +1792,25 @@ multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> { // 1. Extract with offset def : Pat< - (vector_extract vt:$vec, (i64 (zext (add i32:$idx, imm:$off)))), + (vector_extract vt:$vec, (add i32:$idx, imm:$off)), (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off)) >; // 2. Extract without offset def : Pat< - (vector_extract vt:$vec, (i64 (zext i32:$idx))), + (vector_extract vt:$vec, i32:$idx), (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) >; // 3. Insert with offset def : Pat< - (vector_insert vt:$vec, f32:$val, (i64 (zext (add i32:$idx, imm:$off)))), + (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)), (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) >; // 4. Insert without offset def : Pat< - (vector_insert vt:$vec, f32:$val, (i64 (zext i32:$idx))), + (vector_insert vt:$vec, f32:$val, i32:$idx), (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) >; } |