Revert r131664 and fix it in instcombine instead. rdar://9467055

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 31 insertions, 33 deletions

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index e9a9963..2c90aa2 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -1182,7 +1182,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
   bool IsStructRet    = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
   bool IsSibCall = false;
   // Temporarily disable tail calls so things don't break.
-  if (!EnableARMTailCalls)
+  if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
     isTailCall = false;
   if (isTailCall) {
     // Check if it's really possible to do a tail call.
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index c6f266b..0509d58 100644
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -46,6 +46,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
   , PostRAScheduler(false)
   , IsR9Reserved(ReserveR9)
   , UseMovt(false)
+  , SupportsTailCall(false)
   , HasFP16(false)
   , HasD16(false)
   , HasHardwareDivide(false)
@@ -153,6 +154,8 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
   else {
     IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
     UseMovt = DarwinUseMOVT && hasV6T2Ops();
+    const Triple &T = getTargetTriple();
+    SupportsTailCall = T.getOS() == Triple::IOS && !T.isOSVersionLT(5, 0);
   }
 
   if (!isThumb() || hasThumb2())
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h
index 0271c87..c149410 100644
--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@@ -87,6 +87,11 @@ protected:
   /// imms (including global addresses).
   bool UseMovt;
 
+  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
+  /// must be able to synthesize call stubs for interworking between ARM and
+  /// Thumb.
+  bool SupportsTailCall;
+
   /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
   /// only so far)
   bool HasFP16;
@@ -217,6 +222,7 @@ protected:
   bool isR9Reserved() const { return IsR9Reserved; }
 
   bool useMovt() const { return UseMovt && hasV6T2Ops(); }
+  bool supportsTailCall() const { return SupportsTailCall; }
 
   bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
 
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 88f5d31..e5156f8 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -10939,19 +10939,6 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
     KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
                                        Mask.getBitWidth() - 1);
     break;
-
-  case ISD::INTRINSIC_WO_CHAIN: {
-    unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
-    switch (IntNo) {
-      default: break;
-      case Intrinsic::x86_sse42_crc64_8:
-      case Intrinsic::x86_sse42_crc64_64:
-        // crc32 with 64-bit destination zeros high 32-bit.
-        KnownZero |= APInt::getHighBitsSet(64, 32);
-        break;
-    }
-    break;
-  }
   }
 }
 
diff --git a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 9863ceb..e3a117f 100644
--- a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -780,6 +780,10 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
         // TODO: Could compute known zero/one bits based on the input.
         break;
       }
+      case Intrinsic::x86_sse42_crc64_8:
+      case Intrinsic::x86_sse42_crc64_64:
+        KnownZero = APInt::getHighBitsSet(64, 32);
+        return 0;
       }
     }
     ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth);
diff --git a/test/CodeGen/X86/crc64.ll b/test/CodeGen/X86/crc64.ll
deleted file mode 100644
index 1e0aa0d..0000000
--- a/test/CodeGen/X86/crc64.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: llc < %s -march=x86-64 -mattr=sse42 | FileCheck %s
-
-; crc32 with 64-bit destination zeros high 32-bit.
-; rdar://9467055
-
-define i64 @t() nounwind {
-entry:
-; CHECK: t:
-; CHECK: crc32q
-; CHECK-NOT: mov
-; CHECK-NEXT: crc32q
-  %0 = tail call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 4) nounwind
-  %1 = and i64 %0, 4294967295
-  %2 = tail call i64 @llvm.x86.sse42.crc64.64(i64 %1, i64 4) nounwind
-  %3 = and i64 %2, 4294967295
-  ret i64 %3
-}
-
-declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone
diff --git a/test/Transforms/InstCombine/x86-crc32-demanded.ll b/test/Transforms/InstCombine/x86-crc32-demanded.ll
new file mode 100644
index 0000000..be257ac
--- /dev/null
+++ b/test/Transforms/InstCombine/x86-crc32-demanded.ll
@@ -0,0 +1,17 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; crc32 with 64-bit destination zeros high 32-bit.
+; rdar://9467055
+
+define i64 @test() nounwind {
+entry:
+; CHECK: test
+; CHECK: tail call i64 @llvm.x86.sse42.crc64.64
+; CHECK-NOT: and
+; CHECK: ret
+  %0 = tail call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 4) nounwind
+  %1 = and i64 %0, 4294967295
+  ret i64 %1
+}
+
+declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone