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authorBill Wendling <isanbard@gmail.com>2010-11-29 01:07:48 +0000
committerBill Wendling <isanbard@gmail.com>2010-11-29 01:07:48 +0000
commit2f17bf2a4406d89b5e127306cbd0fc862e0a6bd5 (patch)
treec83af692114db428d8cbbc61ee41ebe8af01cebc
parent5cbbf68e35a053c904548564da13d4a8596f988b (diff)
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Add more Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120279 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrThumb.td42
-rw-r--r--test/MC/ARM/thumb.s8
2 files changed, 38 insertions, 12 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 0a53bbb..3af8934 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -1177,24 +1177,42 @@ def tSXTH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
// test
let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
-def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iTSTr,
- "tst", "\t$lhs, $rhs",
- [(ARMcmpZ (and_su tGPR:$lhs, tGPR:$rhs), 0)]>,
- T1DataProcessing<0b1000>;
+def tTST : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
+ "tst", "\t$Rn, $Rm",
+ [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
+ T1DataProcessing<0b1000> {
+ // A8.6.230
+ bits<3> Rm;
+ bits<3> Rn;
+ let Inst{5-3} = Rm;
+ let Inst{2-0} = Rn;
+}
// zero-extend byte
-def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
- "uxtb", "\t$dst, $src",
- [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
+def tUXTB : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
+ "uxtb", "\t$Rd, $Rm",
+ [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
Requires<[IsThumb, IsThumb1Only, HasV6]>,
- T1Misc<{0,0,1,0,1,1,?}>;
+ T1Misc<{0,0,1,0,1,1,?}> {
+ // A8.6.262
+ bits<3> Rm;
+ bits<3> Rd;
+ let Inst{5-3} = Rm;
+ let Inst{2-0} = Rd;
+}
// zero-extend short
-def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
- "uxth", "\t$dst, $src",
- [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
+def tUXTH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
+ "uxth", "\t$Rd, $Rm",
+ [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
Requires<[IsThumb, IsThumb1Only, HasV6]>,
- T1Misc<{0,0,1,0,1,0,?}>;
+ T1Misc<{0,0,1,0,1,0,?}> {
+ // A8.6.264
+ bits<3> Rm;
+ bits<3> Rd;
+ let Inst{5-3} = Rm;
+ let Inst{2-0} = Rd;
+}
// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
diff --git a/test/MC/ARM/thumb.s b/test/MC/ARM/thumb.s
index 386dcfe..2db97c3 100644
--- a/test/MC/ARM/thumb.s
+++ b/test/MC/ARM/thumb.s
@@ -24,3 +24,11 @@
@ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2]
sxtb r2, r3
sxth r2, r3
+
+@ CHECK: tst r4, r5 @ encoding: [0x2c,0x42]
+ tst r4, r5
+
+@ CHECK: uxtb r3, r6 @ encoding: [0xf3,0xb2]
+@ CHECK: uxth r3, r6 @ encoding: [0xb3,0xb2]
+ uxtb r3, r6
+ uxth r3, r6