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author | Jim Grosbach <grosbach@apple.com> | 2011-08-08 23:28:47 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2011-08-08 23:28:47 +0000 |
commit | 3148a654909e55e8511a1c23991bf0ae8d3f9204 (patch) | |
tree | bfe7103585e9763af21df9de212624e65888a00d | |
parent | 648f9a75fdbba228e89389c34a2b3f1ceecd06be (diff) | |
download | external_llvm-3148a654909e55e8511a1c23991bf0ae8d3f9204.zip external_llvm-3148a654909e55e8511a1c23991bf0ae8d3f9204.tar.gz external_llvm-3148a654909e55e8511a1c23991bf0ae8d3f9204.tar.bz2 |
ARM parsing and encoding for LDRBT instruction.
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 39 | ||||
-rw-r--r-- | test/MC/ARM/arm-memory-instructions.s | 16 |
2 files changed, 44 insertions, 11 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 3f683d8..28d6f9f 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2034,20 +2034,37 @@ def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb), let Inst{11-0} = addr{11-0}; let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2"; } -def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb), - (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru, - "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> { - // {17-14} Rn - // {13} 1 == Rm, 0 == imm12 + +def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), + (ins addr_offset_none:$addr, am2offset_reg:$offset), + IndexModePost, LdFrm, IIC_iLoad_bh_ru, + "ldrbt", "\t$Rt, $addr, $offset", + "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm - bits<18> addr; - let Inst{25} = addr{13}; - let Inst{23} = addr{12}; + bits<14> offset; + bits<4> addr; + let Inst{25} = 1; + let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite - let Inst{19-16} = addr{17-14}; - let Inst{11-0} = addr{11-0}; - let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2"; + let Inst{19-16} = addr; + let Inst{11-0} = offset{11-0}; +} + +def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), + (ins addr_offset_none:$addr, am2offset_imm:$offset), + IndexModePost, LdFrm, IIC_iLoad_bh_ru, + "ldrbt", "\t$Rt, $addr, $offset", + "$addr.base = $Rn_wb", []> { + // {12} isAdd + // {11-0} imm12/Rm + bits<14> offset; + bits<4> addr; + let Inst{25} = 0; + let Inst{23} = offset{12}; + let Inst{21} = 1; // overwrite + let Inst{19-16} = addr; + let Inst{11-0} = offset{11-0}; } multiclass AI3ldrT<bits<4> op, string opc> { diff --git a/test/MC/ARM/arm-memory-instructions.s b/test/MC/ARM/arm-memory-instructions.s index 965d8e9..961f24f 100644 --- a/test/MC/ARM/arm-memory-instructions.s +++ b/test/MC/ARM/arm-memory-instructions.s @@ -89,3 +89,19 @@ _func: @ CHECK: ldr r8, [r4], -r5 @ encoding: [0x05,0x80,0x14,0xe6] @ CHECK: ldr r7, [r12, -r1, lsl #15] @ encoding: [0x81,0x77,0x1c,0xe7] @ CHECK: ldr r5, [r2], r9, asr #15 @ encoding: [0xc9,0x57,0x92,0xe6] + + +@------------------------------------------------------------------------------ +@ LDRBT +@------------------------------------------------------------------------------ +@ FIXME: Optional offset operand. + ldrbt r3, [r1], #4 + ldrbt r2, [r8], #-8 + ldrbt r8, [r7], r6 + ldrbt r1, [r2], -r6, lsl #12 + + +@ CHECK: ldrbt r3, [r1], #4 @ encoding: [0x04,0x30,0xf1,0xe4] +@ CHECK: ldrbt r2, [r8], #-8 @ encoding: [0x08,0x20,0x78,0xe4] +@ CHECK: ldrbt r8, [r7], r6 @ encoding: [0x06,0x80,0xf7,0xe6] +@ CHECK: ldrbt r1, [r2], -r6, lsl #12 @ encoding: [0x06,0x16,0x72,0xe6] |