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author | Nadav Rotem <nadav.rotem@intel.com> | 2012-01-03 22:12:28 +0000 |
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committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-01-03 22:12:28 +0000 |
commit | 316477dd543b5ae30b832ed4c7708f7aaa51747c (patch) | |
tree | 93d71834cc15ecc4429742eaee50817be930be9b | |
parent | 3d1161e9ae2aedc45f40cc1b7be1db3df2094903 (diff) | |
download | external_llvm-316477dd543b5ae30b832ed4c7708f7aaa51747c.zip external_llvm-316477dd543b5ae30b832ed4c7708f7aaa51747c.tar.gz external_llvm-316477dd543b5ae30b832ed4c7708f7aaa51747c.tar.bz2 |
Fix incorrect widening of the bitcast sdnode in case the incoming operand is integer-promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147484 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 6 | ||||
-rw-r--r-- | test/CodeGen/X86/promote.ll | 11 |
2 files changed, 17 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 7ca0d1e..6b267c3 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1571,6 +1571,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { case TargetLowering::TypeLegal: break; case TargetLowering::TypePromoteInteger: + // If the incoming type is a vector that is being promoted, then + // we know that the elements are arranged differently and that we + // must perform the conversion using a stack slot. + if (InVT.isVector()) + break; + // If the InOp is promoted to the same size, convert it. Otherwise, // fall out of the switch and widen the promoted input. InOp = GetPromotedInteger(InOp); diff --git a/test/CodeGen/X86/promote.ll b/test/CodeGen/X86/promote.ll index b8964f2..8b30dc7 100644 --- a/test/CodeGen/X86/promote.ll +++ b/test/CodeGen/X86/promote.ll @@ -29,3 +29,14 @@ entry: ret i32 0 ; CHECK: ret } + +; CHECK: bitcast_widen +define <2 x float> @bitcast_widen(<4 x i32> %in) nounwind readnone { +entry: +; CHECK-NOT: pshufd + %x = shufflevector <4 x i32> %in, <4 x i32> undef, <2 x i32> <i32 0, i32 1> + %y = bitcast <2 x i32> %x to <2 x float> + ret <2 x float> %y +; CHECK: ret +} + |