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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-18 20:09:55 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-18 20:09:55 +0000 |
commit | 3560dd2dcd67d42eeb8e59975581d598d71669df (patch) | |
tree | 518c73d7a58dc375519d301a21419de310fd1997 | |
parent | 9bc4b2c0dae143e72624984dfd5e3a4ff2e95eb2 (diff) | |
download | external_llvm-3560dd2dcd67d42eeb8e59975581d598d71669df.zip external_llvm-3560dd2dcd67d42eeb8e59975581d598d71669df.tar.gz external_llvm-3560dd2dcd67d42eeb8e59975581d598d71669df.tar.bz2 |
R600/SI: Fix moveToVALU when the first operand is VSrc.
Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/R600/SIInstrInfo.cpp | 4 | ||||
-rw-r--r-- | lib/Target/R600/SIRegisterInfo.cpp | 2 | ||||
-rw-r--r-- | test/CodeGen/R600/add_i64.ll | 21 |
3 files changed, 14 insertions, 13 deletions
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 7f23ecf..ab55c1b 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -417,7 +417,6 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const { MachineOperand &MO = MI->getOperand(OpIdx); MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass; - // XXX - This shouldn't be VSrc const TargetRegisterClass *RC = RI.getRegClass(RCID); unsigned Opcode = AMDGPU::V_MOV_B32_e32; if (MO.isReg()) { @@ -426,7 +425,8 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const { Opcode = AMDGPU::S_MOV_B32; } - unsigned Reg = MRI.createVirtualRegister(RI.getRegClass(RCID)); + const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); + unsigned Reg = MRI.createVirtualRegister(VRC); BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode), Reg).addOperand(MO); MO.ChangeToRegister(Reg, false); diff --git a/lib/Target/R600/SIRegisterInfo.cpp b/lib/Target/R600/SIRegisterInfo.cpp index 97c216d..ed0bbaf 100644 --- a/lib/Target/R600/SIRegisterInfo.cpp +++ b/lib/Target/R600/SIRegisterInfo.cpp @@ -100,6 +100,8 @@ const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass( const TargetRegisterClass *SRC) const { if (hasVGPRs(SRC)) { return SRC; + } else if (SRC == &AMDGPU::SCCRegRegClass) { + return &AMDGPU::VCCRegRegClass; } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) { return &AMDGPU::VReg_32RegClass; } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) { diff --git a/test/CodeGen/R600/add_i64.ll b/test/CodeGen/R600/add_i64.ll index c5c2a11..303a1cb 100644 --- a/test/CodeGen/R600/add_i64.ll +++ b/test/CodeGen/R600/add_i64.ll @@ -18,26 +18,25 @@ define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noa ret void } -; SI-LABEL: @one_sgpr: -define void @one_sgpr(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) { +; Check that the SGPR add operand is correctly moved to a VGPR. +; SI-LABEL: @sgpr_operand: +define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) { %foo = load i64 addrspace(1)* %in, align 8 %result = add i64 %foo, %a store i64 %result, i64 addrspace(1)* %out ret void } -; FIXME: This case is broken -; ; Swap the arguments. Check that the SGPR -> VGPR copy works with the ; SGPR as other operand. ; -; XXXSI-LABEL: @one_sgpr_reversed: -; define void @one_sgpr_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) { -; %foo = load i64 addrspace(1)* %in, align 8 -; %result = add i64 %a, %foo -; store i64 %result, i64 addrspace(1)* %out -; ret void -; } +; SI-LABEL: @sgpr_operand_reversed: +define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) { + %foo = load i64 addrspace(1)* %in, align 8 + %result = add i64 %a, %foo + store i64 %result, i64 addrspace(1)* %out + ret void +} ; SI-LABEL: @test_v2i64_sreg: |