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| author | Cameron Zwarich <zwarich@apple.com> | 2011-05-21 04:13:49 +0000 |
|---|---|---|
| committer | Cameron Zwarich <zwarich@apple.com> | 2011-05-21 04:13:49 +0000 |
| commit | 37fed38ec155705803250273467d5bec66e0dcd5 (patch) | |
| tree | 1fe31c4db4fa0e8ebfd72220041ca649e99f9064 | |
| parent | 52106e1e25cc87fa3bc7240c68ad7539822c2b16 (diff) | |
| download | external_llvm-37fed38ec155705803250273467d5bec66e0dcd5.zip external_llvm-37fed38ec155705803250273467d5bec66e0dcd5.tar.gz external_llvm-37fed38ec155705803250273467d5bec66e0dcd5.tar.bz2 | |
Fix PR9978 by adding RIP to GR64_TC so it can be used as an address in PIC code. It
is already in GR64 for the same reasons. Since it isn't allocatable it can't cause
any problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131787 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index fd7a247..4bf9699 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -496,7 +496,7 @@ def GR32_TC : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX]> { let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)]; } def GR64_TC : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI, - R8, R9, R11]> { + R8, R9, R11, RIP]> { let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit), (GR32_TC sub_32bit)]; |