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| author | Jim Grosbach <grosbach@apple.com> | 2010-05-05 20:47:15 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-05-05 20:47:15 +0000 |
| commit | 3a548e717feda86847e088a25c65de6c4ada4f95 (patch) | |
| tree | a9ec5cff24ffe39911eaaaa4e78252a348a3a4c8 | |
| parent | b1dc393bd56365ad8fabb51f22c2f3ace707c39a (diff) | |
| download | external_llvm-3a548e717feda86847e088a25c65de6c4ada4f95.zip external_llvm-3a548e717feda86847e088a25c65de6c4ada4f95.tar.gz external_llvm-3a548e717feda86847e088a25c65de6c4ada4f95.tar.bz2 | |
Add tests for ARMV7M divide instruction use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103120 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | test/CodeGen/ARM/div.ll | 28 | ||||
| -rw-r--r-- | test/CodeGen/Thumb2/div.ll | 45 |
2 files changed, 64 insertions, 9 deletions
diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll index 2048ee6..95f8c5f 100644 --- a/test/CodeGen/ARM/div.ll +++ b/test/CodeGen/ARM/div.ll @@ -1,33 +1,43 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECK-ARM +; RUN: llc < %s -march=arm -mcpu=cortex-m3 \ +; RUN: | FileCheck %s -check-prefix=CHECK-ARMV7M define i32 @f1(i32 %a, i32 %b) { entry: -; CHECK: f1 -; CHECK: __divsi3 +; CHECK-ARM: f1 +; CHECK-ARM: __divsi3 +; CHECK-ARMV7M: f1 +; CHECK-ARMV7M: sdiv %tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @f2(i32 %a, i32 %b) { entry: -; CHECK: f2 -; CHECK: __udivsi3 +; CHECK-ARM: f2 +; CHECK-ARM: __udivsi3 +; CHECK-ARMV7M: _f2 +; CHECK-ARMV7M: udiv %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @f3(i32 %a, i32 %b) { entry: -; CHECK: f3 -; CHECK: __modsi3 +; CHECK-ARM: f3 +; CHECK-ARM: __modsi3 +; CHECK-ARMV7M: _f3 +; CHECK-ARMV7M: sdiv %tmp1 = srem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @f4(i32 %a, i32 %b) { entry: -; CHECK: f4 -; CHECK: __umodsi3 +; CHECK-ARM: f4 +; CHECK-ARM: __umodsi3 +; CHECK-ARMV7M: _f4 +; CHECK-ARMV7M: udiv %tmp1 = urem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } diff --git a/test/CodeGen/Thumb2/div.ll b/test/CodeGen/Thumb2/div.ll new file mode 100644 index 0000000..f846e46 --- /dev/null +++ b/test/CodeGen/Thumb2/div.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -march=thumb -mattr=+thumb2 \ +; RUN: | FileCheck %s -check-prefix=CHECK-THUMB +; RUN: llc < %s -march=arm -mcpu=cortex-m3 -mattr=+thumb2 \ +; RUN: | FileCheck %s -check-prefix=CHECK-THUMBV7M + +define i32 @f1(i32 %a, i32 %b) { +entry: +; CHECK-THUMB: f1 +; CHECK-THUMB: __divsi3 +; CHECK-THUMBV7M: f1 +; CHECK-THUMBV7M: sdiv + %tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1] + ret i32 %tmp1 +} + +define i32 @f2(i32 %a, i32 %b) { +entry: +; CHECK-THUMB: f2 +; CHECK-THUMB: __udivsi3 +; CHECK-THUMBV7M: _f2 +; CHECK-THUMBV7M: udiv + %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] + ret i32 %tmp1 +} + +define i32 @f3(i32 %a, i32 %b) { +entry: +; CHECK-THUMB: f3 +; CHECK-THUMB: __modsi3 +; CHECK-THUMBV7M: _f3 +; CHECK-THUMBV7M: sdiv + %tmp1 = srem i32 %a, %b ; <i32> [#uses=1] + ret i32 %tmp1 +} + +define i32 @f4(i32 %a, i32 %b) { +entry: +; CHECK-THUMB: f4 +; CHECK-THUMB: __umodsi3 +; CHECK-THUMBV7M: _f4 +; CHECK-THUMBV7M: udiv + %tmp1 = urem i32 %a, %b ; <i32> [#uses=1] + ret i32 %tmp1 +} + |