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authorJim Grosbach <grosbach@apple.com>2011-03-11 23:15:02 +0000
committerJim Grosbach <grosbach@apple.com>2011-03-11 23:15:02 +0000
commit3c5edaaf59dc051c6d540dd1041cf6bbbb12854f (patch)
treef1b667a89fff30675dcd2e82ee31972b9ce55d74
parent5380bbf6069fc3e71d01c10c8bf139124a50216a (diff)
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Remove dead code. These ARM instruction definitions no longer exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127509 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp2
-rw-r--r--utils/TableGen/ARMDecoderEmitter.cpp8
2 files changed, 1 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index edf7438..8ef44d1 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -2168,7 +2168,7 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
// Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
// Pattern complexity = 6 cost = 11 size = 0
//
- // Also FCPYScc and FCPYDcc.
+ // Also VMOVScc and VMOVDcc.
SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
unsigned Opc = 0;
diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp
index 4c08187..3f2c55f 100644
--- a/utils/TableGen/ARMDecoderEmitter.cpp
+++ b/utils/TableGen/ARMDecoderEmitter.cpp
@@ -1592,14 +1592,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
// better off using the generic RSCri and RSCrs instructions.
if (Name == "RSCSri" || Name == "RSCSrs") return false;
- // FCYPScc, FCYPDcc, FNEGScc, and FNEGDcc are used in the compiler
- // to implement conditional moves. We can ignore them in favor of
- // their more generic versions of instructions. See also
- // SDNode *ARMDAGToDAGISel::Select(SDValue Op).
- if (Name == "FCPYScc" || Name == "FCPYDcc" || Name == "FNEGScc" ||
- Name == "FNEGDcc")
- return false;
-
// Bcc is in a more generic form than B. Ignore B when decoding.
if (Name == "B") return false;