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author | Tom Stellard <thomas.stellard@amd.com> | 2012-12-17 15:14:54 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2012-12-17 15:14:54 +0000 |
commit | 3ee6391e0cddf8d94e2fa441d661c23e494a8489 (patch) | |
tree | 09b968b7662f0697c78b60c38c446da7f897444c | |
parent | ab8ada34c0dcb2381bfd6858461479fffb0c7992 (diff) | |
download | external_llvm-3ee6391e0cddf8d94e2fa441d661c23e494a8489.zip external_llvm-3ee6391e0cddf8d94e2fa441d661c23e494a8489.tar.gz external_llvm-3ee6391e0cddf8d94e2fa441d661c23e494a8489.tar.bz2 |
R600: BB operand support for SI
Patch by: Christian König
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170342 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/R600/AMDGPUMCInstLower.cpp | 10 | ||||
-rw-r--r-- | lib/Target/R600/AMDGPUMCInstLower.h | 5 | ||||
-rw-r--r-- | lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp | 10 | ||||
-rw-r--r-- | lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp | 6 |
4 files changed, 27 insertions, 4 deletions
diff --git a/lib/Target/R600/AMDGPUMCInstLower.cpp b/lib/Target/R600/AMDGPUMCInstLower.cpp index de4053e..32275a2b 100644 --- a/lib/Target/R600/AMDGPUMCInstLower.cpp +++ b/lib/Target/R600/AMDGPUMCInstLower.cpp @@ -21,11 +21,14 @@ #include "llvm/Constants.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCExpr.h" #include "llvm/Support/ErrorHandling.h" using namespace llvm; -AMDGPUMCInstLower::AMDGPUMCInstLower() { } +AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx): + Ctx(ctx) +{ } void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { OutMI.setOpcode(MI->getOpcode()); @@ -50,13 +53,16 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { case MachineOperand::MO_Register: MCOp = MCOperand::CreateReg(MO.getReg()); break; + case MachineOperand::MO_MachineBasicBlock: + MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( + MO.getMBB()->getSymbol(), Ctx)); } OutMI.addOperand(MCOp); } } void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { - AMDGPUMCInstLower MCInstLowering; + AMDGPUMCInstLower MCInstLowering(OutContext); if (MI->isBundle()) { const MachineBasicBlock *MBB = MI->getParent(); diff --git a/lib/Target/R600/AMDGPUMCInstLower.h b/lib/Target/R600/AMDGPUMCInstLower.h index d7bf827..d7d538e 100644 --- a/lib/Target/R600/AMDGPUMCInstLower.h +++ b/lib/Target/R600/AMDGPUMCInstLower.h @@ -14,12 +14,15 @@ namespace llvm { class MCInst; +class MCContext; class MachineInstr; class AMDGPUMCInstLower { + MCContext &Ctx; + public: - AMDGPUMCInstLower(); + AMDGPUMCInstLower(MCContext &ctx); /// \brief Lower a MachineInstr to an MCInst void lower(const MachineInstr *MI, MCInst &OutMI) const; diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp b/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp index 3417fbc..8f41ebb 100644 --- a/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -47,7 +47,7 @@ public: virtual AMDGPUMCObjectWriter *createObjectWriter(raw_ostream &OS) const; virtual unsigned getNumFixupKinds() const { return 0; }; virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, - uint64_t Value) const { assert(!"Not implemented"); } + uint64_t Value) const; virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCInstFragment *DF, const MCAsmLayout &Layout) const { @@ -80,3 +80,11 @@ AMDGPUMCObjectWriter * AMDGPUAsmBackend::createObjectWriter( raw_ostream &OS) const { return new AMDGPUMCObjectWriter(OS); } + +void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, + unsigned DataSize, uint64_t Value) const { + + uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset()); + assert(Fixup.getKind() == FK_PCRel_4); + *Dst = (Value - 4) / 4; +} diff --git a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp index 7f271d1..c47dc99 100644 --- a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp @@ -21,6 +21,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCFixup.h" #include "llvm/Support/raw_ostream.h" #define VGPR_BIT(src_idx) (1ULL << (9 * src_idx - 1)) @@ -149,6 +150,11 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, } Imm; Imm.F = MO.getFPImm(); return Imm.I; + } else if (MO.isExpr()) { + const MCExpr *Expr = MO.getExpr(); + MCFixupKind Kind = MCFixupKind(FK_PCRel_4); + Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); + return 0; } else{ llvm_unreachable("Encoding of this operand type is not supported yet."); } |