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| author | Craig Topper <craig.topper@gmail.com> | 2012-04-24 06:36:35 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-04-24 06:36:35 +0000 |
| commit | 3ef43cf3a2d7fd933f9f9b2960df9426b054d32a (patch) | |
| tree | a9c83911dfb2b873e0eb42882344400ca1b4fd98 | |
| parent | 7fd5e16d3bc24a8ec54c7b48f68b5fed53bfd2e6 (diff) | |
| download | external_llvm-3ef43cf3a2d7fd933f9f9b2960df9426b054d32a.zip external_llvm-3ef43cf3a2d7fd933f9f9b2960df9426b054d32a.tar.gz external_llvm-3ef43cf3a2d7fd933f9f9b2960df9426b054d32a.tar.bz2 | |
Remove dangling spaces. Fix some other formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155429 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 074f96f..e16367a 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -13014,7 +13014,8 @@ SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, if (!DCI.isBeforeLegalizeOps()) return SDValue(); - if (!Subtarget->hasAVX()) return SDValue(); + if (!Subtarget->hasAVX()) + return SDValue(); EVT VT = N->getValueType(0); SDValue Op = N->getOperand(0); @@ -14856,7 +14857,7 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, if (!DCI.isBeforeLegalizeOps()) return SDValue(); - if (!Subtarget->hasAVX()) + if (!Subtarget->hasAVX()) return SDValue(); EVT VT = N->getValueType(0); @@ -14867,9 +14868,8 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { - if (Subtarget->hasAVX2()) { + if (Subtarget->hasAVX2()) return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op); - } // Optimize vectors in AVX mode // Sign extend v8i16 to v8i32 and @@ -14882,21 +14882,23 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, unsigned NumElems = OpVT.getVectorNumElements(); SmallVector<int,8> ShufMask1(NumElems, -1); - for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i; + for (unsigned i = 0; i != NumElems/2; ++i) + ShufMask1[i] = i; SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), &ShufMask1[0]); SmallVector<int,8> ShufMask2(NumElems, -1); - for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2; + for (unsigned i = 0; i != NumElems/2; ++i) + ShufMask2[i] = i + NumElems/2; SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), &ShufMask2[0]); - EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), + EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), VT.getVectorNumElements()/2); - OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); + OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); |