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author | Robert Wilhelm <robert.wilhelm@gmx.net> | 2013-09-28 13:42:22 +0000 |
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committer | Robert Wilhelm <robert.wilhelm@gmx.net> | 2013-09-28 13:42:22 +0000 |
commit | 3f4f420ab7acb10221ba971543a7eed5489fb626 (patch) | |
tree | d5b748cdf5567c17cb13fc823a5d7bc6ec9814e0 | |
parent | f80a63fa23862e578de919f4b44d4fcdee68fd0d (diff) | |
download | external_llvm-3f4f420ab7acb10221ba971543a7eed5489fb626.zip external_llvm-3f4f420ab7acb10221ba971543a7eed5489fb626.tar.gz external_llvm-3f4f420ab7acb10221ba971543a7eed5489fb626.tar.bz2 |
Even more spelling fixes for "instruction".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/CodeGen/LiveInterval.h | 2 | ||||
-rw-r--r-- | include/llvm/CodeGen/MachineBasicBlock.h | 4 | ||||
-rw-r--r-- | include/llvm/CodeGen/ScheduleDAGInstrs.h | 2 | ||||
-rw-r--r-- | include/llvm/Target/TargetSchedule.td | 2 | ||||
-rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 2 | ||||
-rw-r--r-- | lib/Target/ARM/Thumb1RegisterInfo.cpp | 2 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonInstrFormats.td | 2 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonPeephole.cpp | 2 | ||||
-rw-r--r-- | lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 2 | ||||
-rw-r--r-- | lib/Target/Mips/MipsAnalyzeImmediate.h | 10 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 2 | ||||
-rw-r--r-- | lib/Target/R600/AMDGPUIndirectAddressing.cpp | 2 | ||||
-rw-r--r-- | lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 2 | ||||
-rw-r--r-- | lib/Transforms/Vectorize/LoopVectorize.cpp | 4 | ||||
-rw-r--r-- | lib/Transforms/Vectorize/SLPVectorizer.cpp | 2 |
15 files changed, 21 insertions, 21 deletions
diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index eb2030f..005b154 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -66,7 +66,7 @@ namespace llvm { } /// Returns true if this value is defined by a PHI instruction (or was, - /// PHI instrucions may have been eliminated). + /// PHI instructions may have been eliminated). /// PHI-defs begin at a block boundary, all other defs begin at register or /// EC slots. bool isPHIDef() const { return def.isBlock(); } diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h index e126f86..7717809 100644 --- a/include/llvm/CodeGen/MachineBasicBlock.h +++ b/include/llvm/CodeGen/MachineBasicBlock.h @@ -410,8 +410,8 @@ public: /// branch to do so (e.g., a table jump). True is a conservative answer. bool canFallThrough(); - /// Returns a pointer to the first instructon in this block that is not a - /// PHINode instruction. When adding instruction to the beginning of the + /// Returns a pointer to the first instruction in this block that is not a + /// PHINode instruction. When adding instructions to the beginning of the /// basic block, they should be added before the returned value, not before /// the first instruction, which might be PHI. /// Returns end() is there's no non-PHI instruction. diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h index 999f2d3..fe4f3c2 100644 --- a/include/llvm/CodeGen/ScheduleDAGInstrs.h +++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h @@ -129,7 +129,7 @@ namespace llvm { Reg2SUnitsMap Defs; Reg2SUnitsMap Uses; - /// Track the last instructon in this region defining each virtual register. + /// Track the last instruction in this region defining each virtual register. VReg2SUnitMap VRegDefs; /// PendingLoads - Remember where unknown loads are after the most recent diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td index e81a2fb..9d4858a 100644 --- a/include/llvm/Target/TargetSchedule.td +++ b/include/llvm/Target/TargetSchedule.td @@ -76,7 +76,7 @@ def instregex; // See MCSchedule.h for detailed comments. class SchedMachineModel { int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. - int MinLatency = -1; // Determines which instrucions are allowed in a group. + int MinLatency = -1; // Determines which instructions are allowed in a group. // (-1) inorder (0) ooo, (1): inorder +var latencies. int MicroOpBufferSize = -1; // Max micro-ops that can be buffered. int LoadLatency = -1; // Cycles for loads to access the cache. diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index cedfc6d..2f7f1bf 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -847,7 +847,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, case ARM::MOVsrl_flag: case ARM::MOVsra_flag: { - // These are just fancy MOVs insructions. + // These are just fancy MOVs instructions. AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), MI.getOperand(0).getReg()) .addOperand(MI.getOperand(1)) diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 6722614..954e3f5 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -426,7 +426,7 @@ rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, *this); } else { // Translate r0 = add sp, -imm to - // r0 = -imm (this is then translated into a series of instructons) + // r0 = -imm (this is then translated into a series of instructions) // r0 = add r0, sp emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl); diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index e71386a..d25bfa8 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -63,7 +63,7 @@ class MemAccessSize<bits<3> value> { def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction. def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb). def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh). -def WordAccess : MemAccessSize<3>;// Word access instrution (memw). +def WordAccess : MemAccessSize<3>;// Word access instruction (memw). def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd) diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp index 89e3406..5490ecd 100644 --- a/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/lib/Target/Hexagon/HexagonPeephole.cpp @@ -29,7 +29,7 @@ // // Note: The peephole pass makes the instrucstions like // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill> -// redundant and relies on some form of dead removal instrucions, like +// redundant and relies on some form of dead removal instructions, like // DCE or DIE to actually eliminate them. diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index e0f5a27..8519cf3 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -73,7 +73,7 @@ namespace HexagonII { NoMemAccess = 0, // Not a memory acces instruction. ByteAccess = 1, // Byte access instruction (memb). HalfWordAccess = 2, // Half word access instruction (memh). - WordAccess = 3, // Word access instrution (memw). + WordAccess = 3, // Word access instruction (memw). DoubleWordAccess = 4 // Double word access instruction (memd) }; diff --git a/lib/Target/Mips/MipsAnalyzeImmediate.h b/lib/Target/Mips/MipsAnalyzeImmediate.h index a094dda..cc09034 100644 --- a/lib/Target/Mips/MipsAnalyzeImmediate.h +++ b/lib/Target/Mips/MipsAnalyzeImmediate.h @@ -22,7 +22,7 @@ namespace llvm { }; typedef SmallVector<Inst, 7 > InstSeq; - /// Analyze - Get an instrucion sequence to load immediate Imm. The last + /// Analyze - Get an instruction sequence to load immediate Imm. The last /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is /// true; const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu); @@ -32,19 +32,19 @@ namespace llvm { /// AddInstr - Add I to all instruction sequences in SeqLs. void AddInstr(InstSeqLs &SeqLs, const Inst &I); - /// GetInstSeqLsADDiu - Get instrucion sequences which end with an ADDiu to + /// GetInstSeqLsADDiu - Get instruction sequences which end with an ADDiu to /// load immediate Imm void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); - /// GetInstSeqLsORi - Get instrucion sequences which end with an ORi to + /// GetInstSeqLsORi - Get instrutcion sequences which end with an ORi to /// load immediate Imm void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); - /// GetInstSeqLsSLL - Get instrucion sequences which end with a SLL to + /// GetInstSeqLsSLL - Get instruction sequences which end with a SLL to /// load immediate Imm void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); - /// GetInstSeqLs - Get instrucion sequences to load immediate Imm. + /// GetInstSeqLs - Get instruction sequences to load immediate Imm. void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi. diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index be6d753..1f80289 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -115,7 +115,7 @@ def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, // Wrapper node patterns give the instruction selector a chance to replace // target constant nodes that would otherwise remain unchanged with ADDiu // nodes. Without these wrapper node patterns, the following conditional move -// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is +// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is // compiled: // movn %got(d)($gp), %got(c)($gp), $4 // This instruction is illegal since movn can take only register operands. diff --git a/lib/Target/R600/AMDGPUIndirectAddressing.cpp b/lib/Target/R600/AMDGPUIndirectAddressing.cpp index 3ce3ecf..f31eed0 100644 --- a/lib/Target/R600/AMDGPUIndirectAddressing.cpp +++ b/lib/Target/R600/AMDGPUIndirectAddressing.cpp @@ -275,7 +275,7 @@ bool AMDGPUIndirectAddressingPass::runOnMachineFunction(MachineFunction &MF) { } else { // Indirect register access - // Note on REQ_SEQUENCE instructons: You can't actually use the register + // Note on REQ_SEQUENCE instructions: You can't actually use the register // it defines unless you have an instruction that takes the defined // register class as an operand. diff --git a/lib/Transforms/Scalar/LoopIdiomRecognize.cpp b/lib/Transforms/Scalar/LoopIdiomRecognize.cpp index 32af415..952b76b 100644 --- a/lib/Transforms/Scalar/LoopIdiomRecognize.cpp +++ b/lib/Transforms/Scalar/LoopIdiomRecognize.cpp @@ -314,7 +314,7 @@ bool NclPopcountRecognize::preliminaryScreen() { if (TTI->getPopcntSupport(32) != TargetTransformInfo::PSK_FastHardware) return false; - // Counting population are usually conducted by few arithmetic instrutions. + // Counting population are usually conducted by few arithmetic instructions. // Such instructions can be easilly "absorbed" by vacant slots in a // non-compact loop. Therefore, recognizing popcount idiom only makes sense // in a compact loop. diff --git a/lib/Transforms/Vectorize/LoopVectorize.cpp b/lib/Transforms/Vectorize/LoopVectorize.cpp index 4833aec..e8c245e 100644 --- a/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -1357,7 +1357,7 @@ void InnerLoopVectorizer::scalarizeInstruction(Instruction *Instr) { Instruction *Cloned = Instr->clone(); if (!IsVoidRetTy) Cloned->setName(Instr->getName() + ".cloned"); - // Replace the operands of the cloned instrucions with extracted scalars. + // Replace the operands of the cloned instructions with extracted scalars. for (unsigned op = 0, e = Instr->getNumOperands(); op != e; ++op) { Value *Op = Params[op][Part]; // Param is a vector. Need to extract the right lane. @@ -4901,7 +4901,7 @@ void InnerLoopUnroller::scalarizeInstruction(Instruction *Instr) { Instruction *Cloned = Instr->clone(); if (!IsVoidRetTy) Cloned->setName(Instr->getName() + ".cloned"); - // Replace the operands of the cloned instrucions with extracted scalars. + // Replace the operands of the cloned instructions with extracted scalars. for (unsigned op = 0, e = Instr->getNumOperands(); op != e; ++op) { Value *Op = Params[op][Part]; Cloned->setOperand(op, Op); diff --git a/lib/Transforms/Vectorize/SLPVectorizer.cpp b/lib/Transforms/Vectorize/SLPVectorizer.cpp index ae202c2..2b0bdfa 100644 --- a/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -318,7 +318,7 @@ private: /// \returns the pointer to the barrier instruction if we can't sink. Value *getSinkBarrier(Instruction *Src, Instruction *Dst); - /// \returns the index of the last instrucion in the BB from \p VL. + /// \returns the index of the last instruction in the BB from \p VL. int getLastIndex(ArrayRef<Value *> VL); /// \returns the Instruction in the bundle \p VL. |