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| author | Evan Cheng <evan.cheng@apple.com> | 2010-11-03 00:40:22 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-11-03 00:40:22 +0000 |
| commit | 41957f6eb2271e5f1981b32a873d1b58217c6411 (patch) | |
| tree | 454532643a4154de45f211dd4ea2b7512c606607 | |
| parent | 5005e27f9714f0eaa5b8b7a5a1f6751afa163f07 (diff) | |
| download | external_llvm-41957f6eb2271e5f1981b32a873d1b58217c6411.zip external_llvm-41957f6eb2271e5f1981b32a873d1b58217c6411.tar.gz external_llvm-41957f6eb2271e5f1981b32a873d1b58217c6411.tar.bz2 | |
Modify scheduling itineraries to correct instruction latencies (not operand
latencies) of loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118134 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 474 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 154 |
2 files changed, 314 insertions, 314 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index 25bdaa2..94b22c9 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -98,76 +98,76 @@ def CortexA8Itineraries : ProcessorItineraries< // Integer load pipeline // // Immediate offset - InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1]>, - InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1]>, - InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1]>, // // Register offset - InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, - InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, - InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, // // Scaled register offset, issues over 2 cycles // FIXME: lsl by 2 takes 1 cycle. - InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>, - InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>, // // Immediate offset with update - InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>, - InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>, // // Register offset with update - InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, - InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, - InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, // // Scaled register offset with update, issues over 2 cycles - InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>, - InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>, + InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>, + InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>, // // Load multiple, def is the 5th operand. Pipeline 0 only. // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. - InstrItinData<IIC_iLoad_m , [InstrStage<1, [A8_Pipe0]>, + InstrItinData<IIC_iLoad_m , [InstrStage<2, [A8_Pipe0], 0>, InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>, // // Load multiple + update, defs are the 1st and 5th operands. - InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A8_Pipe0]>, + InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>, InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>, // // Load multiple plus branch - InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A8_Pipe0]>, + InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>, InstrStage<3, [A8_LSPipe]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 2, 1, 1, 3]>, // // Pop, def is the 3rd operand. - InstrItinData<IIC_iPop , [InstrStage<1, [A8_Pipe0]>, + InstrItinData<IIC_iPop , [InstrStage<3, [A8_Pipe0], 0>, InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>, // // Push, def is the 3th operand. - InstrItinData<IIC_iPop_Br, [InstrStage<1, [A8_Pipe0]>, + InstrItinData<IIC_iPop_Br, [InstrStage<3, [A8_Pipe0], 0>, InstrStage<3, [A8_LSPipe]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 3]>, // // iLoadi + iALUr for t2LDRpci_pic. - InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>, @@ -175,54 +175,54 @@ def CortexA8Itineraries : ProcessorItineraries< // Integer store pipeline // // Immediate offset - InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1]>, - InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1]>, - InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1]>, // // Register offset - InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, - InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, - InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, // // Scaled register offset, issues over 2 cycles - InstrItinData<IIC_iStore_si , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>, - InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>, // // Immediate offset with update - InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>, - InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>, // // Register offset with update - InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, - InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, - InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, // // Scaled register offset with update, issues over 2 cycles - InstrItinData<IIC_iStore_siu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>, - InstrItinData<IIC_iStore_bh_siu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>, // // Store multiple. Pipeline 0 only. // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. - InstrItinData<IIC_iStore_m , [InstrStage<1, [A8_Pipe0]>, + InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>, InstrStage<2, [A8_LSPipe]>]>, // // Store multiple + update - InstrItinData<IIC_iStore_mu, [InstrStage<1, [A8_Pipe0]>, + InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>, InstrStage<2, [A8_LSPipe]>], [2]>, // Branch @@ -236,224 +236,224 @@ def CortexA8Itineraries : ProcessorItineraries< // possible. // // FP Special Register to Integer Register File Move - InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>], [20]>, // // Single-precision FP Unary - InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [7, 1]>, // // Double-precision FP Unary - InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<4, [A8_NPipe], 0>, InstrStage<4, [A8_NLSPipe]>], [4, 1]>, // // Single-precision FP Compare - InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [1, 1]>, // // Double-precision FP Compare - InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<4, [A8_NPipe], 0>, InstrStage<4, [A8_NLSPipe]>], [4, 1]>, // // Single to Double FP Convert - InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<7, [A8_NPipe], 0>, InstrStage<7, [A8_NLSPipe]>], [7, 1]>, // // Double to Single FP Convert - InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<5, [A8_NPipe], 0>, InstrStage<5, [A8_NLSPipe]>], [5, 1]>, // // Single-Precision FP to Integer Convert - InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [7, 1]>, // // Double-Precision FP to Integer Convert - InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<8, [A8_NPipe], 0>, InstrStage<8, [A8_NLSPipe]>], [8, 1]>, // // Integer to Single-Precision FP Convert - InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [7, 1]>, // // Integer to Double-Precision FP Convert - InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<8, [A8_NPipe], 0>, InstrStage<8, [A8_NLSPipe]>], [8, 1]>, // // Single-precision FP ALU - InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [7, 1, 1]>, // // Double-precision FP ALU - InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<9, [A8_NPipe], 0>, InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>, // // Single-precision FP Multiply - InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [7, 1, 1]>, // // Double-precision FP Multiply - InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<11, [A8_NPipe], 0>, InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>, // // Single-precision FP MAC - InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>, // // Double-precision FP MAC - InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<19, [A8_NPipe], 0>, InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>, // // Single-precision FP DIV - InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<20, [A8_NPipe], 0>, InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>, // // Double-precision FP DIV - InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<29, [A8_NPipe], 0>, InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>, // // Single-precision FP SQRT - InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<19, [A8_NPipe], 0>, InstrStage<19, [A8_NLSPipe]>], [19, 1]>, // // Double-precision FP SQRT - InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<29, [A8_NPipe], 0>, InstrStage<29, [A8_NLSPipe]>], [29, 1]>, // // Integer to Single-precision Move - InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [2, 1]>, // // Integer to Double-precision Move - InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [2, 1, 1]>, // // Single-precision to Integer Move - InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [20, 1]>, // // Double-precision to Integer Move - InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [20, 20, 1]>, // // Single-precision FP Load - InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [2, 1]>, // // Double-precision FP Load - InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [2, 1]>, // // FP Load Multiple // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. - InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, - InstrStage<1, [A8_NLSPipe]>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>, // // FP Load Multiple + update - InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, - InstrStage<1, [A8_NLSPipe]>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>, // // Single-precision FP Store - InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [1, 1]>, // // Double-precision FP Store - InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [1, 1]>, // // FP Store Multiple - InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, - InstrStage<1, [A8_NLSPipe]>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>, // // FP Store Multiple + update - InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, - InstrStage<1, [A8_NLSPipe]>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>, // NEON // Issue through integer pipeline, and execute in NEON unit. // // VLD1 - InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1]>, // VLD1x2 - InstrItinData<IIC_VLD1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 2, 1]>, // // VLD1x3 - InstrItinData<IIC_VLD1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 1]>, // // VLD1x4 - InstrItinData<IIC_VLD1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 1]>, // // VLD1u - InstrItinData<IIC_VLD1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 2, 1]>, // // VLD1x2u - InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 2, 2, 1]>, // // VLD1x3u - InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 2, 1]>, // // VLD1x4u - InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 2, 1]>, // @@ -470,134 +470,134 @@ def CortexA8Itineraries : ProcessorItineraries< [3, 2, 1, 1, 1, 1]>, // // VLD2 - InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 2, 1]>, // // VLD2x2 - InstrItinData<IIC_VLD2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 1]>, // // VLD2ln - InstrItinData<IIC_VLD2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [3, 3, 1, 1, 1, 1]>, // // VLD2u - InstrItinData<IIC_VLD2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 2, 2, 1, 1, 1]>, // // VLD2x2u - InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 2, 1]>, // // VLD2lnu - InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [3, 3, 2, 1, 1, 1, 1, 1]>, // // VLD3 - InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [3, 3, 4, 1]>, // // VLD3ln - InstrItinData<IIC_VLD3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<5, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<5, [A8_NLSPipe], 0>, InstrStage<5, [A8_LSPipe]>], [4, 4, 5, 1, 1, 1, 1, 2]>, // // VLD3u - InstrItinData<IIC_VLD3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [3, 3, 4, 2, 1]>, // // VLD3lnu - InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<5, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<5, [A8_NLSPipe], 0>, InstrStage<5, [A8_LSPipe]>], [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>, // // VLD4 - InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [3, 3, 4, 4, 1]>, // // VLD4ln - InstrItinData<IIC_VLD4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<5, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<5, [A8_NLSPipe], 0>, InstrStage<5, [A8_LSPipe]>], [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>, // // VLD4u - InstrItinData<IIC_VLD4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [3, 3, 4, 4, 2, 1]>, // // VLD4lnu - InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<5, [A8_NLSPipe], 1>, + InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<5, [A8_NLSPipe], 0>, InstrStage<5, [A8_LSPipe]>], [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>, // // VST1 - InstrItinData<IIC_VST1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [1, 1, 1]>, // // VST1x2 - InstrItinData<IIC_VST1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1]>, // // VST1x3 - InstrItinData<IIC_VST1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [1, 1, 1, 1, 2]>, // // VST1x4 - InstrItinData<IIC_VST1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [1, 1, 1, 1, 2, 2]>, // // VST1u - InstrItinData<IIC_VST1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1, 1, 1, 1]>, // // VST1x2u - InstrItinData<IIC_VST1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1]>, // // VST1x3u - InstrItinData<IIC_VST1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2]>, // // VST1x4u - InstrItinData<IIC_VST1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -614,360 +614,360 @@ def CortexA8Itineraries : ProcessorItineraries< [2, 1, 1, 1, 1]>, // // VST2 - InstrItinData<IIC_VST2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1]>, // // VST2x2 - InstrItinData<IIC_VST2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [1, 1, 1, 1, 2, 2]>, // // VST2u - InstrItinData<IIC_VST2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1]>, // // VST2x2u - InstrItinData<IIC_VST2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // // VST2ln - InstrItinData<IIC_VST2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1]>, // // VST2lnu - InstrItinData<IIC_VST2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1]>, // // VST3 - InstrItinData<IIC_VST3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [1, 1, 1, 1, 2]>, // // VST3u - InstrItinData<IIC_VST3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2]>, // // VST3ln - InstrItinData<IIC_VST3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [1, 1, 1, 1, 2]>, // // VST3lnu - InstrItinData<IIC_VST3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2]>, // // VST4 - InstrItinData<IIC_VST4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [1, 1, 1, 1, 2, 2]>, // // VST4u - InstrItinData<IIC_VST4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // // VST4ln - InstrItinData<IIC_VST4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [1, 1, 1, 1, 2, 2]>, // // VST4lnu - InstrItinData<IIC_VST4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData<IIC_VST4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // // Double-register FP Unary - InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [5, 2]>, // // Quad-register FP Unary // Result written in N5, but that is relative to the last cycle of multicycle, // so we use 6 for those cases - InstrItinData<IIC_VUNAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VUNAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [6, 2]>, // // Double-register FP Binary - InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [5, 2, 2]>, // // VPADD, etc. - InstrItinData<IIC_VPBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VPBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [5, 2, 2]>, // // Double-register FP VMUL - InstrItinData<IIC_VFMULD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VFMULD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [5, 2, 1]>, // // Quad-register FP Binary // Result written in N5, but that is relative to the last cycle of multicycle, // so we use 6 for those cases - InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [6, 2, 2]>, // // Quad-register FP VMUL - InstrItinData<IIC_VFMULQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VFMULQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [6, 2, 1]>, // // Move - InstrItinData<IIC_VMOV, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMOV, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [1, 1]>, // // Move Immediate - InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [3]>, // // Double-register Permute Move - InstrItinData<IIC_VMOVD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMOVD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>], [2, 1]>, // // Quad-register Permute Move // Result written in N2, but that is relative to the last cycle of multicycle, // so we use 3 for those cases - InstrItinData<IIC_VMOVQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMOVQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NLSPipe]>], [3, 1]>, // // Integer to Single-precision Move - InstrItinData<IIC_VMOVIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMOVIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>], [2, 1]>, // // Integer to Double-precision Move - InstrItinData<IIC_VMOVID , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMOVID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>, // // Single-precision to Integer Move - InstrItinData<IIC_VMOVSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMOVSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>], [20, 1]>, // // Double-precision to Integer Move - InstrItinData<IIC_VMOVDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMOVDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>, // // Integer to Lane Move - InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>, // // Vector narrow move - InstrItinData<IIC_VMOVN , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMOVN , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [2, 1]>, // // Double-register Permute - InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>, // // Quad-register Permute // Result written in N2, but that is relative to the last cycle of multicycle, // so we use 3 for those cases - InstrItinData<IIC_VPERMQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VPERMQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>, // // Quad-register Permute (3 cycle issue) // Result written in N2, but that is relative to the last cycle of multicycle, // so we use 4 for those cases - InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>, InstrStage<1, [A8_NPipe], 0>, InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>, // // Double-register FP Multiple-Accumulate - InstrItinData<IIC_VMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>, // // Quad-register FP Multiple-Accumulate // Result written in N9, but that is relative to the last cycle of multicycle, // so we use 10 for those cases - InstrItinData<IIC_VMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>, // // Double-register Reciprical Step - InstrItinData<IIC_VRECSD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VRECSD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [9, 2, 2]>, // // Quad-register Reciprical Step - InstrItinData<IIC_VRECSQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VRECSQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [10, 2, 2]>, // // Double-register Integer Count - InstrItinData<IIC_VCNTiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VCNTiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, // // Quad-register Integer Count // Result written in N3, but that is relative to the last cycle of multicycle, // so we use 4 for those cases - InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [4, 2, 2]>, // // Double-register Integer Unary - InstrItinData<IIC_VUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [4, 2]>, // // Quad-register Integer Unary - InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [4, 2]>, // // Double-register Integer Q-Unary - InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [4, 1]>, // // Quad-register Integer CountQ-Unary - InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [4, 1]>, // // Double-register Integer Binary - InstrItinData<IIC_VBINiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VBINiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, // // Quad-register Integer Binary - InstrItinData<IIC_VBINiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VBINiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, // // Double-register Integer Binary (4 cycle) - InstrItinData<IIC_VBINi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VBINi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, // // Quad-register Integer Binary (4 cycle) - InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, // // Double-register Integer Subtract - InstrItinData<IIC_VSUBiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VSUBiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [3, 2, 1]>, // // Quad-register Integer Subtract - InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [3, 2, 1]>, // // Double-register Integer Subtract - InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, // // Quad-register Integer Subtract - InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, // // Double-register Integer Shift - InstrItinData<IIC_VSHLiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VSHLiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [3, 1, 1]>, // // Quad-register Integer Shift - InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [4, 1, 1]>, // // Double-register Integer Shift (4 cycle) - InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [4, 1, 1]>, // // Quad-register Integer Shift (4 cycle) - InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [5, 1, 1]>, // // Double-register Integer Pair Add Long - InstrItinData<IIC_VPALiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VPALiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [6, 3, 1]>, // // Quad-register Integer Pair Add Long - InstrItinData<IIC_VPALiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VPALiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [7, 3, 1]>, // // Double-register Absolute Difference and Accumulate - InstrItinData<IIC_VABAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VABAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>, // // Quad-register Absolute Difference and Accumulate - InstrItinData<IIC_VABAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VABAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>, // // Double-register Integer Multiply (.8, .16) - InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [6, 2, 2]>, // // Double-register Integer Multiply (.32) - InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [7, 2, 1]>, // // Quad-register Integer Multiply (.8, .16) - InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [7, 2, 2]>, // // Quad-register Integer Multiply (.32) - InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>, InstrStage<2, [A8_NLSPipe], 0>, InstrStage<3, [A8_NPipe]>], [9, 2, 1]>, // // Double-register Integer Multiply-Accumulate (.8, .16) - InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>, // // Double-register Integer Multiply-Accumulate (.32) - InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>, // // Quad-register Integer Multiply-Accumulate (.8, .16) - InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>, // // Quad-register Integer Multiply-Accumulate (.32) - InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NPipe]>, InstrStage<2, [A8_NLSPipe], 0>, InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>, // // Double-register VEXT - InstrItinData<IIC_VEXTD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VEXTD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>, // // Quad-register VEXT - InstrItinData<IIC_VEXTQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VEXTQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>, // // VTB - InstrItinData<IIC_VTB1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VTB1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>, - InstrItinData<IIC_VTB2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VTB2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>, - InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>, InstrStage<1, [A8_NPipe], 0>, InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>, - InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>, InstrStage<1, [A8_NPipe], 0>, InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>, // // VTBX - InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>, - InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>, - InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>, InstrStage<1, [A8_NPipe], 0>, InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>, - InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe]>, InstrStage<1, [A8_NPipe], 0>, InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]> diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index fb2c24d..d5ab5dc 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -173,88 +173,88 @@ def CortexA9Itineraries : ProcessorItineraries< // Immediate offset InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 1], [A9_LdBypass]>, // FIXME: If address is 64-bit aligned, AGU cycles is 1. InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 3, 1], [A9_LdBypass]>, // // Register offset InstrItinData<IIC_iLoad_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 3, 1, 1], [A9_LdBypass]>, // // Scaled register offset InstrItinData<IIC_iLoad_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, - InstrStage<1, [A9_LSUnit]>], + InstrStage<1, [A9_AGU], 0>, + InstrStage<1, [A9_LSUnit], 0>], [4, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [5, 1, 1], [A9_LdBypass]>, // // Immediate offset with update InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 2, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 3, 1], [A9_LdBypass]>, // // Register offset with update InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 2, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 3, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 3, 1, 1], [A9_LdBypass]>, // // Scaled register offset with update InstrItinData<IIC_iLoad_siu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 3, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [5, 4, 1, 1], [A9_LdBypass]>, // @@ -305,7 +305,7 @@ def CortexA9Itineraries : ProcessorItineraries< // iLoadi + iALUr for t2LDRpci_pic. InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>, InstrStage<1, [A9_ALU0, A9_ALU1]>], [2, 1]>, @@ -315,7 +315,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Immediate offset InstrItinData<IIC_iStore_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, @@ -330,7 +330,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Register offset InstrItinData<IIC_iStore_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, @@ -344,7 +344,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Scaled register offset InstrItinData<IIC_iStore_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, @@ -354,7 +354,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Immediate offset with update InstrItinData<IIC_iStore_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1]>, InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, @@ -364,7 +364,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Register offset with update InstrItinData<IIC_iStore_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -381,7 +381,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Scaled register offset with update InstrItinData<IIC_iStore_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -393,13 +393,13 @@ def CortexA9Itineraries : ProcessorItineraries< // Store multiple InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<2, [A9_LSUnit]>]>, // // Store multiple + update InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<2, [A9_LSUnit]>], [2]>, // Branch @@ -657,7 +657,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, // @@ -667,7 +667,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1]>, // @@ -676,7 +676,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>, // // FP Load Multiple + update @@ -684,7 +684,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, // // Single-precision FP Store @@ -692,7 +692,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, // @@ -701,7 +701,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, // @@ -710,7 +710,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>, // // FP Store Multiple + update @@ -718,7 +718,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, // NEON // VLD1 @@ -727,7 +727,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1]>, // VLD1x2 @@ -735,7 +735,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 2, 1]>, // VLD1x3 @@ -743,7 +743,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 1]>, // VLD1x4 @@ -751,7 +751,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 3, 1]>, // VLD1u @@ -759,7 +759,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 2, 1]>, // VLD1x2u @@ -767,7 +767,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 2, 2, 1]>, // VLD1x3u @@ -775,7 +775,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 2, 1]>, // VLD1x4u @@ -783,7 +783,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 3, 2, 1]>, // @@ -811,7 +811,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, // Extra latency cycles since wbck is 7 cycles InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [3, 3, 1]>, // @@ -820,7 +820,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [3, 4, 3, 4, 1]>, // @@ -829,7 +829,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [4, 4, 1, 1, 1, 1]>, // @@ -839,7 +839,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, // Extra latency cycles since wbck is 7 cycles InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [3, 3, 2, 1, 1, 1]>, // @@ -848,7 +848,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [3, 4, 3, 4, 2, 1]>, // @@ -857,7 +857,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [4, 4, 2, 1, 1, 1, 1, 1]>, // @@ -866,7 +866,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 1]>, // @@ -875,7 +875,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 1, 1, 1, 1, 2]>, // @@ -884,7 +884,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 2, 1]>, // @@ -893,7 +893,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>, // @@ -902,7 +902,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 5, 1]>, // @@ -911,7 +911,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 6, 1, 1, 1, 1, 2, 2]>, // @@ -920,7 +920,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 5, 2, 1]>, // @@ -929,7 +929,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 6, 2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -938,7 +938,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1]>, // @@ -947,7 +947,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>, // @@ -956,7 +956,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2]>, // @@ -965,7 +965,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -974,7 +974,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1, 1]>, // @@ -983,7 +983,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1]>, // @@ -992,7 +992,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2]>, // @@ -1001,7 +1001,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -1028,7 +1028,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>, // @@ -1037,7 +1037,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -1046,7 +1046,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1]>, // @@ -1055,7 +1055,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -1064,7 +1064,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>, // @@ -1073,7 +1073,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1]>, // @@ -1082,7 +1082,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2]>, // @@ -1091,7 +1091,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2]>, // @@ -1100,7 +1100,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2]>, // @@ -1109,7 +1109,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2]>, // @@ -1118,7 +1118,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -1127,7 +1127,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -1136,7 +1136,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -1145,7 +1145,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, |