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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-09-14 14:42:15 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-09-14 14:42:15 +0000 |
| commit | 436fe8498a0a3368d2690290e805213a0f114d0d (patch) | |
| tree | b7a43539e5f3db823739a9a8c1d90c661bc2b2e7 | |
| parent | a08e255e1e47d732b31262a95a8ba810f85735c4 (diff) | |
| download | external_llvm-436fe8498a0a3368d2690290e805213a0f114d0d.zip external_llvm-436fe8498a0a3368d2690290e805213a0f114d0d.tar.gz external_llvm-436fe8498a0a3368d2690290e805213a0f114d0d.tar.bz2 | |
Add integer promotion support for vselect
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139692 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 9 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 | ||||
| -rw-r--r-- | test/CodeGen/X86/sse41-blend.ll | 17 |
3 files changed, 27 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index de3a568..508ab21 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -64,6 +64,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; + case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; case ISD::SHL: Res = PromoteIntRes_SHL(N); break; @@ -465,6 +466,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { LHS.getValueType(), N->getOperand(0),LHS,RHS); } +SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) { + SDValue Mask = GetPromotedInteger(N->getOperand(0)); + SDValue LHS = GetPromotedInteger(N->getOperand(1)); + SDValue RHS = GetPromotedInteger(N->getOperand(2)); + return DAG.getNode(ISD::VSELECT, N->getDebugLoc(), + LHS.getValueType(), Mask, LHS, RHS); +} + SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { SDValue LHS = GetPromotedInteger(N->getOperand(2)); SDValue RHS = GetPromotedInteger(N->getOperand(3)); diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h index a9523f5..0b8f911 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -240,6 +240,7 @@ private: SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo); SDValue PromoteIntRes_SDIV(SDNode *N); SDValue PromoteIntRes_SELECT(SDNode *N); + SDValue PromoteIntRes_VSELECT(SDNode *N); SDValue PromoteIntRes_SELECT_CC(SDNode *N); SDValue PromoteIntRes_SETCC(SDNode *N); SDValue PromoteIntRes_SHL(SDNode *N); diff --git a/test/CodeGen/X86/sse41-blend.ll b/test/CodeGen/X86/sse41-blend.ll index 5a169dc..a21416b 100644 --- a/test/CodeGen/X86/sse41-blend.ll +++ b/test/CodeGen/X86/sse41-blend.ll @@ -9,6 +9,23 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { } +;CHECK: vsel_4xi8 +;CHECK: blendvps +;CHECK: ret +define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) { + %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i8> %v1, <4 x i8> %v2 + ret <4 x i8> %vsel +} + +;CHECK: vsel_4xi16 +;CHECK: blendvps +;CHECK: ret +define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) { + %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> %v1, <4 x i16> %v2 + ret <4 x i16> %vsel +} + + ;CHECK: vsel_i32 ;CHECK: blendvps ;CHECK: ret |