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author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2013-09-14 06:49:25 +0000 |
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committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2013-09-14 06:49:25 +0000 |
commit | 47b33528d1b4298bf8cc5dcca8b531dfd0e704bb (patch) | |
tree | 3b09b82495b8592175ac7663257fb9ca965b9f6b | |
parent | 58b90b1e38ec6f5d6f11afae1cf3097dc8fb49aa (diff) | |
download | external_llvm-47b33528d1b4298bf8cc5dcca8b531dfd0e704bb.zip external_llvm-47b33528d1b4298bf8cc5dcca8b531dfd0e704bb.tar.gz external_llvm-47b33528d1b4298bf8cc5dcca8b531dfd0e704bb.tar.bz2 |
Support for misc microMIPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190744 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/MicroMipsInstrFormats.td | 42 | ||||
-rw-r--r-- | lib/Target/Mips/MicroMipsInstrInfo.td | 16 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 6 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 26 | ||||
-rw-r--r-- | test/MC/Disassembler/Mips/micromips.txt | 21 | ||||
-rw-r--r-- | test/MC/Disassembler/Mips/micromips_le.txt | 21 |
6 files changed, 116 insertions, 16 deletions
diff --git a/lib/Target/Mips/MicroMipsInstrFormats.td b/lib/Target/Mips/MicroMipsInstrFormats.td index 6d8d29e..0b82ef8 100644 --- a/lib/Target/Mips/MicroMipsInstrFormats.td +++ b/lib/Target/Mips/MicroMipsInstrFormats.td @@ -162,3 +162,45 @@ class MFLO_FM_MM<bits<10> funct> : MMArch { let Inst{15-6} = funct; let Inst{5-0} = 0x3c; } + +class CLO_FM_MM<bits<10> funct> : MMArch { + bits<5> rd; + bits<5> rs; + + bits<32> Inst; + + let Inst{31-26} = 0x00; + let Inst{25-21} = rd; + let Inst{20-16} = rs; + let Inst{15-6} = funct; + let Inst{5-0} = 0x3c; +} + +class SEB_FM_MM<bits<10> funct> : MMArch { + bits<5> rd; + bits<5> rt; + + bits<32> Inst; + + let Inst{31-26} = 0x00; + let Inst{25-21} = rd; + let Inst{20-16} = rt; + let Inst{15-6} = funct; + let Inst{5-0} = 0x3c; +} + +class EXT_FM_MM<bits<6> funct> : MMArch { + bits<5> rt; + bits<5> rs; + bits<5> pos; + bits<5> size; + + bits<32> Inst; + + let Inst{31-26} = 0x00; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-11} = size; + let Inst{10-6} = pos; + let Inst{5-0} = funct; +} diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index eaf2f31..b274d6f 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -135,4 +135,20 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def MADDU_MM : MMRel, MArithR<"maddu", 1>, MULT_FM_MM<0x36c>; def MSUB_MM : MMRel, MArithR<"msub">, MULT_FM_MM<0x3ac>; def MSUBU_MM : MMRel, MArithR<"msubu">, MULT_FM_MM<0x3ec>; + + /// Count Leading + def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>; + def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>; + + /// Sign Ext In Register Instructions. + def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM_MM<0x0ac>; + def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM_MM<0x0ec>; + + /// Word Swap Bytes Within Halfwords + def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>; + + def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, + EXT_FM_MM<0x2c>; + def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, + EXT_FM_MM<0x0c>; } diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index c536264..f0d82dc 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -333,7 +333,7 @@ class MTLO_FM<bits<6> funct> : StdArch { let Inst{5-0} = funct; } -class SEB_FM<bits<5> funct, bits<6> funct2> { +class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch { bits<5> rd; bits<5> rt; @@ -347,7 +347,7 @@ class SEB_FM<bits<5> funct, bits<6> funct2> { let Inst{5-0} = funct2; } -class CLO_FM<bits<6> funct> { +class CLO_FM<bits<6> funct> : StdArch { bits<5> rd; bits<5> rs; bits<5> rt; @@ -424,7 +424,7 @@ class MULT_FM<bits<6> op, bits<6> funct> : StdArch { let Inst{5-0} = funct; } -class EXT_FM<bits<6> funct> { +class EXT_FM<bits<6> funct> : StdArch { bits<5> rt; bits<5> rs; bits<5> pos; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 14d1665..e4b51ce 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -710,26 +710,26 @@ class EffectiveAddress<string opstr, RegisterOperand RO> : // Count Leading Ones/Zeros in Word class CountLeading0<string opstr, RegisterOperand RO>: InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), - [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>, + [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>, Requires<[HasBitCount, HasStdEnc]>; class CountLeading1<string opstr, RegisterOperand RO>: InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), - [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>, + [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>, Requires<[HasBitCount, HasStdEnc]>; // Sign Extend in Register. class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> : InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), - [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> { + [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> { let Predicates = [HasSEInReg, HasStdEnc]; } // Subword Swap class SubwordSwap<string opstr, RegisterOperand RO>: InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], - NoItinerary, FrmR> { + NoItinerary, FrmR, opstr> { let Predicates = [HasSwap, HasStdEnc]; let neverHasSideEffects = 1; } @@ -745,7 +745,7 @@ class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size), !strconcat(opstr, " $rt, $rs, $pos, $size"), [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary, - FrmR> { + FrmR, opstr> { let Predicates = [HasMips32r2, HasStdEnc]; } @@ -754,7 +754,7 @@ class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src), !strconcat(opstr, " $rt, $rs, $pos, $size"), [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))], - NoItinerary, FrmR> { + NoItinerary, FrmR, opstr> { let Predicates = [HasMips32r2, HasStdEnc]; let Constraints = "$src = $rt"; } @@ -1027,15 +1027,15 @@ def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>; def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>; /// Sign Ext In Register Instructions. -def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; -def SEH : SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>; +def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; +def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>; /// Count Leading -def CLZ : CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; -def CLO : CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>; +def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; +def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>; /// Word Swap Bytes Within Halfwords -def WSBH : SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>; +def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>; /// No operation. def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; @@ -1058,8 +1058,8 @@ def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; -def EXT : ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>; -def INS : InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; +def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>; +def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; /// Move Control Registers From/To CPU Registers def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>; diff --git a/test/MC/Disassembler/Mips/micromips.txt b/test/MC/Disassembler/Mips/micromips.txt index 6f70d97..b963b05 100644 --- a/test/MC/Disassembler/Mips/micromips.txt +++ b/test/MC/Disassembler/Mips/micromips.txt @@ -183,3 +183,24 @@ # CHECK: msubu $4, $5 0x00 0xa4 0xfb 0x3c + +# CHECK: clz $9, $6 +0x01 0x26 0x5b 0x3c + +# CHECK: clo $9, $6 +0x01 0x26 0x4b 0x3c + +# CHECK: seb $9, $6 +0x01 0x26 0x2b 0x3c + +# CHECK: seh $9, $6 +0x01 0x26 0x3b 0x3c + +# CHECK: wsbh $9, $6 +0x01 0x26 0x7b 0x3c + +# CHECK: ext $9, $6, 3, 7 +0x01 0x26 0x30 0xec + +# CHECK: ins $9, $6, 3, 7 +0x01 0x26 0x48 0xcc diff --git a/test/MC/Disassembler/Mips/micromips_le.txt b/test/MC/Disassembler/Mips/micromips_le.txt index 9630c17..ef08158 100644 --- a/test/MC/Disassembler/Mips/micromips_le.txt +++ b/test/MC/Disassembler/Mips/micromips_le.txt @@ -183,3 +183,24 @@ # CHECK: msubu $4, $5 0xa4 0x00 0x3c 0xfb + +# CHECK: clz $9, $6 +0x26 0x01 0x3c 0x5b + +# CHECK: clo $9, $6 +0x26 0x01 0x3c 0x4b + +# CHECK: seb $9, $6 +0x26 0x01 0x3c 0x2b + +# CHECK: seh $9, $6 +0x26 0x01 0x3c 0x3b + +# CHECK: wsbh $9, $6 +0x26 0x01 0x3c 0x7b + +# CHECK: ext $9, $6, 3, 7 +0x26 0x01 0xec 0x30 + +# CHECK: ins $9, $6, 3, 7 +0x26 0x01 0xcc 0x48 |