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| author | Eric Christopher <echristo@apple.com> | 2012-05-07 06:25:15 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2012-05-07 06:25:15 +0000 |
| commit | 4adbefebd2eeeab4d7007b697b4cc20e40ba06b8 (patch) | |
| tree | a7b39d03b16fd42f35e4064cb72a4b0041c6034c | |
| parent | 1d5a392e2cff41488e47e038231fb114ea0eb941 (diff) | |
| download | external_llvm-4adbefebd2eeeab4d7007b697b4cc20e40ba06b8.zip external_llvm-4adbefebd2eeeab4d7007b697b4cc20e40ba06b8.tar.gz external_llvm-4adbefebd2eeeab4d7007b697b4cc20e40ba06b8.tar.bz2 | |
Add support for the 'l' constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156294 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll | 11 |
2 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 854cfab..ca0472b 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -3001,6 +3001,7 @@ getConstraintType(const std::string &Constraint) const // backwards compatibility. // 'c' : A register suitable for use in an indirect // jump. This will always be $25 for -mabicalls. + // 'l' : The lo register. if (Constraint.size() == 1) { switch (Constraint[0]) { default : break; @@ -3008,6 +3009,7 @@ getConstraintType(const std::string &Constraint) const case 'y': case 'f': case 'c': + case 'l': return C_RegisterClass; } } @@ -3042,6 +3044,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight( weight = CW_Register; break; case 'c': // $25 for indirect jumps + case 'l': // lo register if (type->isIntegerTy()) weight = CW_SpecificReg; break; @@ -3090,6 +3093,10 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass); assert(VT == MVT::i64 && "Unexpected type."); return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass); + case 'l': // register suitable for indirect jump + if (VT == MVT::i32) + return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass); + return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass); } } return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll index aa186ec..94ded30 100644 --- a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll @@ -29,5 +29,16 @@ entry: ; CHECK: #NO_APP tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind +; Now l with 1024: make sure register lo is picked. We do this by checking the instruction +; after the inline expression for a mflo to pull the value out of lo. +; CHECK: #APP +; CHECK-NEXT: mtlo ${{[0-9]+}} +; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}} +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: mflo ${{[0-9]+}} + %bosco = alloca i32, align 4 + call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind + store volatile i32 %4, i32* %bosco, align 4 + ret i32 0 } |