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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-07-16 20:58:34 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-07-16 20:58:34 +0000 |
| commit | 4c769c3c06d763b4db82231211c80d5aa9be45b5 (patch) | |
| tree | d0fab0c87edcb0916f1a2e0733d49895c4161336 | |
| parent | 6dbb7f62ad93f4034dff2825dd4d1f33c667cc5a (diff) | |
| download | external_llvm-4c769c3c06d763b4db82231211c80d5aa9be45b5.zip external_llvm-4c769c3c06d763b4db82231211c80d5aa9be45b5.tar.gz external_llvm-4c769c3c06d763b4db82231211c80d5aa9be45b5.tar.bz2 | |
Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.
The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76101 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/MachineInstr.cpp | 20 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll | 16 |
2 files changed, 28 insertions, 8 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 98cc767..c6f3e31 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -783,16 +783,20 @@ isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { const MachineOperand &MO = getOperand(UseOpIdx); if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) return false; - int FlagIdx = UseOpIdx - 1; - if (FlagIdx < 1) - return false; - while (!getOperand(FlagIdx).isImm()) { - if (--FlagIdx == 0) - return false; + + // Find the flag operand corresponding to UseOpIdx + unsigned FlagIdx, NumOps=0; + for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) { + const MachineOperand &UFMO = getOperand(FlagIdx); + assert(UFMO.isImm() && "Expecting flag operand on inline asm"); + NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm()); + assert(NumOps < getNumOperands() && "Invalid inline asm flag"); + if (UseOpIdx < FlagIdx+NumOps+1) + break; } - const MachineOperand &UFMO = getOperand(FlagIdx); - if (FlagIdx + InlineAsm::getNumOperandRegisters(UFMO.getImm()) < UseOpIdx) + if (FlagIdx >= UseOpIdx) return false; + const MachineOperand &UFMO = getOperand(FlagIdx); unsigned DefNo; if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { if (!DefOpIdx) diff --git a/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll b/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll new file mode 100644 index 0000000..d636e80 --- /dev/null +++ b/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -verify-machineinstrs + +; Machine code verifier will call isRegTiedToDefOperand() on /all/ register use +; operands. We must make sure that the operand flag is found correctly. + +; This test case is actually not specific to PowerPC, but the (imm, reg) format +; of PowerPC "m" operands trigger this bug. + +define void @memory_asm_operand(i32 %a) { + ; "m" operand will be represented as: + ; INLINEASM <es:fake $0>, 10, %R2, 20, -4, %R1 + ; It is difficult to find the flag operand (20) when starting from %R1 + call i32 asm "lbzx $0, $1", "=r,m" (i32 %a) + ret void +} + |