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author | Arnold Schwaighofer <arnold.schwaighofer@gmail.com> | 2008-09-22 14:50:07 +0000 |
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committer | Arnold Schwaighofer <arnold.schwaighofer@gmail.com> | 2008-09-22 14:50:07 +0000 |
commit | 4da27f66ca01a88277d8370617b2aebd5763ef3f (patch) | |
tree | 8c33aa2a19ad9ed57f4947b227592e2fdbbeffe0 | |
parent | c821c87af4285fb9f8dec3b1f0084b588ece00ba (diff) | |
download | external_llvm-4da27f66ca01a88277d8370617b2aebd5763ef3f.zip external_llvm-4da27f66ca01a88277d8370617b2aebd5763ef3f.tar.gz external_llvm-4da27f66ca01a88277d8370617b2aebd5763ef3f.tar.bz2 |
Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56436 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86CallingConv.td | 16 | ||||
-rw-r--r-- | lib/Target/X86/X86FastISel.cpp | 2 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 6 | ||||
-rw-r--r-- | test/CodeGen/X86/tailcall-stackalign.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/tailcallbyval.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/tailcallfp2.ll | 2 |
6 files changed, 5 insertions, 25 deletions
diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td index e720b0b..b98b5d9 100644 --- a/lib/Target/X86/X86CallingConv.td +++ b/lib/Target/X86/X86CallingConv.td @@ -312,22 +312,6 @@ def CC_X86_32_C : CallingConv<[ CCDelegateTo<CC_X86_32_Common> ]>; -/// Same as C calling convention except for non-free ECX which is used for storing -/// a potential pointer to the tail called function. -def CC_X86_32_TailCall : CallingConv<[ - // Promote i8/i16 arguments to i32. - CCIfType<[i8, i16], CCPromoteToType<i32>>, - - // Nested function trampolines are currently not supported by fastcc. - - // The first 3 integer arguments, if marked 'inreg' and if the call is not - // a vararg call, are passed in integer registers. - CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>>>, - - // Otherwise, same as everything else. - CCDelegateTo<CC_X86_32_Common> -]>; - def CC_X86_32_FastCall : CallingConv<[ // Promote i8/i16 arguments to i32. CCIfType<[i8, i16], CCPromoteToType<i32>>, diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 3d27ff3..7747788 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -142,8 +142,6 @@ CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) { if (CC == CallingConv::X86_FastCall) return CC_X86_32_FastCall; - else if (CC == CallingConv::Fast && isTaillCall) - return CC_X86_32_TailCall; else if (CC == CallingConv::Fast) return CC_X86_32_FastCC; else diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 3401a2c..78121bd 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -890,7 +890,7 @@ SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { SDValue TargetAddress = TailCall.getOperand(1); SDValue StackAdjustment = TailCall.getOperand(2); assert(((TargetAddress.getOpcode() == ISD::Register && - (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX || + (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX || cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) || TargetAddress.getOpcode() == ISD::TargetExternalSymbol || TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && @@ -1098,8 +1098,6 @@ CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const { if (CC == CallingConv::X86_FastCall) return CC_X86_32_FastCall; - else if (CC == CallingConv::Fast && PerformTailCallOpt) - return CC_X86_32_TailCall; else if (CC == CallingConv::Fast) return CC_X86_32_FastCC; else @@ -1700,7 +1698,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); } else if (IsTailCall) { - unsigned Opc = Is64Bit ? X86::R9 : X86::ECX; + unsigned Opc = Is64Bit ? X86::R9 : X86::EAX; Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Opc, getPointerTy()), diff --git a/test/CodeGen/X86/tailcall-stackalign.ll b/test/CodeGen/X86/tailcall-stackalign.ll index 8011192..ff960b8 100644 --- a/test/CodeGen/X86/tailcall-stackalign.ll +++ b/test/CodeGen/X86/tailcall-stackalign.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=i686-unknown-linux -tailcallopt | grep -A 1 call | grep -A 1 tailcaller | grep subl | grep 20 +; RUN: llvm-as < %s | llc -mtriple=i686-unknown-linux -tailcallopt | grep -A 1 call | grep -A 1 tailcaller | grep subl | grep 12 ; Linux has 8 byte alignment so the params cause stack size 20 when tailcallopt ; is enabled, ensure that a normal fastcc call has matching stack size diff --git a/test/CodeGen/X86/tailcallbyval.ll b/test/CodeGen/X86/tailcallbyval.ll index 9085b05..112a497 100644 --- a/test/CodeGen/X86/tailcallbyval.ll +++ b/test/CodeGen/X86/tailcallbyval.ll @@ -1,6 +1,6 @@ ; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep TAILCALL ; check for the 2 byval moves -; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep rep | wc -l | grep 2 +; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep movl | grep ecx | grep eax | wc -l | grep 1 %struct.s = type {i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } diff --git a/test/CodeGen/X86/tailcallfp2.ll b/test/CodeGen/X86/tailcallfp2.ll index 4fa01f6..151701e 100644 --- a/test/CodeGen/X86/tailcallfp2.ll +++ b/test/CodeGen/X86/tailcallfp2.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep {jmp} | grep {\\*%ecx} +; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep {jmp} | grep {\\*%eax} declare i32 @putchar(i32) |