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| author | Eli Friedman <eli.friedman@gmail.com> | 2011-08-29 18:23:02 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2011-08-29 18:23:02 +0000 |
| commit | 4db5acaf48c119b2bb7ad93b10dfcfe8b58dcfdb (patch) | |
| tree | 3a5f6e620fc5adb87f6bd1efbfb40053ed58df11 | |
| parent | 7e0d22cbf7b41e93279f574c9b3c557cdf517dcb (diff) | |
| download | external_llvm-4db5acaf48c119b2bb7ad93b10dfcfe8b58dcfdb.zip external_llvm-4db5acaf48c119b2bb7ad93b10dfcfe8b58dcfdb.tar.gz external_llvm-4db5acaf48c119b2bb7ad93b10dfcfe8b58dcfdb.tar.bz2 | |
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 3 |
4 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index ccb84ab..ca8f2db 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -596,6 +596,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use // the default expansion. + // FIXME: This should be checking for v6k, not just v6. if (Subtarget->hasDataBarrier() || (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { // membarrier needs custom lowering; the rest are legal and handled diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 8fb6340..68ae715 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -153,6 +153,9 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) setOperationAction(ISD::JumpTable, MVT::i64, Custom); setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); + setStackPointerRegisterToSaveRestore(Alpha::R30); setJumpBufSize(272); diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 9ddf66c..3e1e009 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -178,6 +178,9 @@ MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); + setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); + setInsertFencesForAtomic(true); if (Subtarget->isSingleFloat()) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 78a75f9..f3917c4 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -365,6 +365,9 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); } + setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); + setBooleanContents(ZeroOrOneBooleanContent); if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { |