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authorZhou Sheng <zhousheng00@gmail.com>2008-06-06 08:32:05 +0000
committerZhou Sheng <zhousheng00@gmail.com>2008-06-06 08:32:05 +0000
commit533604e367c255a7ad43d1857231db7abf360581 (patch)
tree04fa4a15c399e0d7749ebe0aa26308231be17c0a
parentba221ca2410097537bad9d3a346ae9eb8e332e7c (diff)
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As Chris suggested, handle the situation if ShAmt larger than BitWidth,
otherwise, opt might crash. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52041 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Transforms/Scalar/InstructionCombining.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index 05e1269..67c40fe 100644
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -1236,7 +1236,7 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask,
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
- if (BitWidth == ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] ||
+ if (BitWidth <= ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] ||
(HighBits & ~DemandedMask) == HighBits) {
// Perform the logical shift right.
Value *NewVal = BinaryOperator::CreateLShr(