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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-14 08:06:38 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-14 08:06:38 +0000 |
| commit | 54f009f5a427c640266d223826eed851a8a340c3 (patch) | |
| tree | 5028b3cf34765cfa82416c4ae917bf6ef4167abb | |
| parent | a837ac357cf1354eba301665f643d7e95e26cd51 (diff) | |
| download | external_llvm-54f009f5a427c640266d223826eed851a8a340c3.zip external_llvm-54f009f5a427c640266d223826eed851a8a340c3.tar.gz external_llvm-54f009f5a427c640266d223826eed851a8a340c3.tar.bz2 | |
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194684 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index e293c3a..8eb707d 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -440,7 +440,9 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { // Legalize VOP2 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) { MachineOperand &Src1 = MI->getOperand(Src1Idx); - // Legalize VOP2 instructions where src1 is not a VGPR. + + // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must + // be the first operand, and there can only be one. if (Src1.isImm() || Src1.isFPImm() || (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) { if (MI->isCommutable()) { |